公开(公告)号：US09207937B2

公开(公告)日：2015-12-08

申请号：US13137948

申请日：2011-09-22

申请人： David James Seal ,  Richard Roy Grisenthwaite ,  Nigel John Stephens

发明人： David James Seal ,  Richard Roy Grisenthwaite ,  Nigel John Stephens

IPC分类号： G06F9/30 ,  G06F7/76

CPC分类号： G06F9/3016 ,  G06F7/764 ,  G06F7/768 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/3887

摘要： A data processing apparatus comprises a processing circuit and instruction decoder. A bitfield manipulation instruction controls the processing apparatus to generate at least one result data element from corresponding first and second source data elements. Each result data element includes a portion corresponding to a bitfield bf of the corresponding first source data element. Bits of the result data element that are more significant than the inserted bitfield have a prefix value that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element, and a third prefix value corresponding to a sign extension of the bitfield of the first source data element.

摘要翻译： 数据处理装置包括处理电路和指令译码器。 位
域操作指令控制处理装置，从对应的第一和第二源数据元素生成至少一个结果数据元素。 每个结果数据元素包括对应于相应的第一源数据元素的位字段bf的部分。 结果数据元素比插入的位域更重要的位具有基于由指令指定的控制值而被选择的前缀值作为具有零值的第一前缀值之一，具有第二前缀值的前缀值具有 相应的第二源数据元素的一部分的值，以及与第一源数据元素的位域的符号扩展对应的第三前缀值。

公开(公告)号：US20120233444A1

公开(公告)日：2012-09-13

申请号：US13353805

申请日：2012-01-19

申请人： Nigel John Stephens ,  David James Seal

发明人： Nigel John Stephens ,  David James Seal

IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F9/345 ,  G06F9/302

CPC分类号： G06F9/30149 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/3016 ,  G06F9/30192 ,  G06F9/345 ,  G06F9/355

摘要： A data processing system 2 includes a processor core 4 and a memory 6. The processor core 4 includes processing circuitry 12, 14, 16, 18, 26 controlled by control signals generated by decoder circuitry 24 which decodes program instructions. The program instructions include mixed operand size instructions (either load/store instructions or arithmetic instructions) which have a first input operand of a first operand size and a second input operand of a second input operand size where the second operand size is smaller than the first operand size. The processing performed first converts the second operand so as to have the first operand size. The processing then generates a third operand using as inputs the first operand of the first operand size and the second operand now converted to have the first operand size.

摘要翻译： 数据处理系统2包括处理器核心4和存储器6.处理器核心4包括由解码器电路24产生的控制信号控制的处理电路12,14,16,18,26，其解码程序指令。 程序指令包括具有第一操作数大小的第一输入操作数和第二输入操作数大小的第二输入操作数的混合操作数大小指令（加载/存储指令或算术指令），其中第二操作数大小小于第一操作数大小 操作数大小。 所执行的处理首先将第二操作数转换为具有第一操作数大小。 然后，处理使用第一操作数大小的第一操作数作为输入并且现在转换为具有第一操作数大小的第二操作数作为输入产生第三操作数。

公开(公告)号：US20120233440A1

公开(公告)日：2012-09-13

申请号：US13361229

申请日：2012-01-30

申请人： Nigel John Stephens ,  David James Seal

发明人： Nigel John Stephens ,  David James Seal

IPC分类号： G06F12/00

CPC分类号： G06F9/3557 ,  G06F9/30007 ,  G06F9/30112 ,  G06F9/30167 ,  G06F9/342 ,  G06F9/345 ,  G06F2212/657

摘要： A data processing apparatus is provided comprising processing circuitry and an instruction decoder responsive to program instructions to control processing circuitry to perform the data processing. The instruction decoder is responsive to an address calculating instruction to perform an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value such that a full address specifying a memory location of an information entity is calculable from said partial address result using at least one supplementary program instruction. The partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction. A corresponding data processing method, virtual machine and computer program product are also provided.

摘要翻译： 提供了一种数据处理装置，其包括响应于程序指令的处理电路和指令解码器，以控制处理电路执行数据处理。 指令解码器响应于地址计算指令来执行地址计算操作，用于从非固定参考地址和部分偏移值计算部分地址结果，使得可以从...计算指定信息实体的存储位置的完整地址 所述部分地址结果使用至少一个补充程序指令。 部分偏移值具有大于或等于所述指令大小的位宽，并且被编码在所述地址计算指令的至少一个部分偏移字段内。 还提供了相应的数据处理方法，虚拟机和计算机程序产品。

公开(公告)号：US20110231633A1

公开(公告)日：2011-09-22

申请号：US13064257

申请日：2011-03-14

申请人： Richard Roy Grisenthwaite ,  David James Seal ,  Philippe Jean-Pierre Raphalen ,  Lee Douglas Smith

发明人： Richard Roy Grisenthwaite ,  David James Seal ,  Philippe Jean-Pierre Raphalen ,  Lee Douglas Smith

IPC分类号： G06F9/30

CPC分类号： G06F9/3016 ,  G06F9/3001 ,  G06F9/30112 ,  G06F9/3861 ,  G06F21/577 ,  G06F21/70 ,  G06F2221/2145

摘要： A data processing system 2 is provided with processing circuitry 8, 10, 12 as well as a bank of 64-bit registers 6. An instruction decoder 14 decodes arithmetic instructions and logical instruction specifying arithmetic operations and logical operations to be performed upon operands stored within the 64-bit registers 6. The instruction decoder 14 is responsive to an operand size field SF within the arithmetic instructions and the logical instructions specifying whether the operands are 64-bit operands or 32-bit operands. Each 64-bit register stores either a single 64-bit operand or a single 32-bit operand. For a given arithmetic instruction and logical instruction either all of the operands are 64-bit operands or all of the operands are 32-bit operands. A plurality of exception levels arranged in a hierarchy of exception levels may be supported. If a switch is made to a lower exception level, then a check is made as to whether or not a register being used was previously subject to a 64-bit write to that register. If such a 64-bit write had previously taken place to that register, then the upper 32-bits are flushed so as to avoid data leakage from the higher exception level.

摘要翻译： 数据处理系统2设置有处理电路8,10,12以及一组64位寄存器6.指令译码器14解码算术指令和指定算术运算的逻辑指令和对存储在其中的操作数执行的逻辑运算 64位寄存器6.指令解码器14响应于算术指令内的操作数大小字段SF，逻辑指令指定操作数是64位操作数还是32位操作数。 每个64位寄存器存储单个64位操作数或单个32位操作数。 对于给定的算术指令和逻辑指令，所有操作数都是64位操作数，或者所有操作数都是32位操作数。 可以支持以异常级别分层布置的多个异常级别。 如果将交换机设置为较低的异常级别，则检查所使用的寄存器是否先前对该寄存器进行64位写操作。 如果先前对该寄存器进行了这样的64位写操作，则高位32位被刷新，以避免数据从较高异常级别泄漏。

公开(公告)号：US20110225397A1

公开(公告)日：2011-09-15

申请号：US12929865

申请日：2011-02-22

申请人： Richard Roy Grisenthwaite ,  David James Seal

发明人： Richard Roy Grisenthwaite ,  David James Seal

IPC分类号： G06F9/30

CPC分类号： G06F9/30112 ,  G06F9/30123 ,  G06F9/30138 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/384 ,  G06F9/3863

摘要： A processor 4 is provided which supports a first instruction set specifying 32-bit architectural registers and a second instruction set specifying 64-bit architectural registers. Each of these instruction sets is presented with its own set of architectural registers for use. The first set of registers presented to the first instruction set has a one-to-one mapping to the second set of registers presented to this second instruction set. The registers which are provided in hardware are 64-bit registers. In some embodiments, when executing program instructions of the first instruction set, only the least significant portion of these 64-bit registers are accessed and manipulated with the remaining most significant portion of the registers being left unaltered. Register specifying fields within instructions of the first instruction set are decoded together with a current exception mode to determine which architectural register to use whereas the second instruction set uses register specifying fields without a dependence upon exception mode to determine which architectural register are to be used.

摘要翻译： 提供处理器4，其支持指定32位架构寄存器的第一指令集和指定64位架构寄存器的第二指令集。 这些指令集中的每一个都带有自己的一组架构寄存器供使用。 呈现给第一指令集的第一组寄存器具有与呈现给该第二指令集的第二组寄存器的一对一映射。 在硬件中提供的寄存器是64位寄存器。 在一些实施例中，当执行第一指令集的程序指令时，只有这些64位寄存器的最低有效部分被访问和操作，其中最重要的寄存器部分保持不变。 在第一指令集的指令内的寄存器指定字段与当前异常模式一起被解码以确定要使用的架构寄存器，而第二指令集使用寄存器指定字段而不依赖于异常模式来确定要使用哪个架构寄存器。

公开(公告)号：US07788472B2

公开(公告)日：2010-08-31

申请号：US10781883

申请日：2004-02-20

申请人： David James Seal ,  Edward Colles Nevill

发明人： David James Seal ,  Edward Colles Nevill

IPC分类号： G06F9/30

CPC分类号： G06F9/30196 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3822 ,  G06F9/3885

摘要： A data processing apparatus 2 is provided which supports two instruction sets. These two instruction sets share a common subset of instructions including at least one class of instructions, such as all of the coprocessor instructions. The common subset of instructions have the same instruction encoding once any differences due to storage order within memory have been compensated for e.g. endianness.

摘要翻译： 提供了支持两个指令集的数据处理装置2。 这两个指令集共享包括至少一类指令（例如所有协处理器指令）的公共指令子集。 一旦由于存储器内的存储顺序导致的任何差异已被补偿，例如，指令的共同子集具有相同的指令编码。 字符串

公开(公告)号：US07178011B2

公开(公告)日：2007-02-13

申请号：US10765867

申请日：2004-01-29

申请人： David James Seal ,  Vladimir Vasekin

发明人： David James Seal ,  Vladimir Vasekin

IPC分类号： G06F9/40

CPC分类号： G06F9/30072 ,  G06F9/30058 ,  G06F9/30181

摘要： Within a data processing system, prediction instructions are provided which add conditional behaviour to associated program instructions.

摘要翻译： 在数据处理系统中，提供预测指令，其向相关程序指令添加条件行为。

公开(公告)号：US07047401B2

公开(公告)日：2006-05-16

申请号：US10461335

申请日：2003-06-16

申请人： David James Seal ,  Richard Roy Grisenthwaite

发明人： David James Seal ,  Richard Roy Grisenthwaite

IPC分类号： G06F9/312

CPC分类号： G06F9/30043 ,  G06F9/3861

摘要： A data processing apparatus 2 supports multiple memory access program instructions LDM, STM which serve to load data values from multiple program registers 16 to respective memory locations or to store data values from multiple memory locations to respective program registers. A memory management unit 8 within the system stores device or strongly ordered memory attribute values which control whether or not a multiple memory access instruction involving such a memory location may be early terminated when an interrupt is received during its operation. Early termination is permitted in those circumstances where the multiple memory access instruction may be safely restarted and rerun in its entirety, whereas early termination is not permitted and the operation completes before the interrupt is taken in those circumstances where the memory locations are subject to a guaranteed number of memory accesses as this appears within the controlling program instructions.

摘要翻译： 数据处理装置2支持用于将来自多个程序寄存器16的数据值加载到相应存储器位置的多个存储器访问程序指令LDM，STM或将多个存储器位置的数据值存储到各个程序寄存器。 系统内的存储器管理单元8存储设备或强有序的存储器属性值，其控制在其操作期间接收到中断时是否可能提前终止涉及这样的存储器位置的多存储器访问指令。 在多重内存访问指令可以安全地重新启动并全部重新运行的情况下，允许提前终止，而不允许提前终止，并且在内存位置受到保证的情况下中断之前，操作完成 存储器访问次数显示在控制程序指令内。

公开(公告)号：US06542916B1

公开(公告)日：2003-04-01

申请号：US09362182

申请日：1999-07-28

申请人： Christopher Neal Hinds ,  David Vivian Jaggar ,  David James Seal

发明人： Christopher Neal Hinds ,  David Vivian Jaggar ,  David James Seal

IPC分类号： G06F738

CPC分类号： G06F7/5443 ,  G06F7/483 ,  G06F7/49947

摘要： A data processing apparatus and method is provided for applying a floating-point multiply-accumulate operation to first, second and third operands. The apparatus comprises a multiplier for multiplying the second and third operands and applying rounding to produce a rounded multiplication result, and an adder for adding the rounded multiplication result to the first operand to generate a final result and for applying rounding to generate a rounded final result. Further, control logic is provided which is responsive to a first single instruction to control the multiplier and adder to cause the rounded final result generated by the adder to be equivalent to the subtraction of the rounded multiplication result from the first operand. In preferred embodiments, the control logic is also responsive to a further single instruction to control the multiplier and adder to cause the rounded final result generated by the adder to be equivalent to the subtraction of the rounded multiplication result from the negated first operand. By this approach, multiply-accumulate logic can be arranged to provide fast execution of a first single instruction to generate a result equivalent to the subtraction of the rounded multiplication result from the first operand, or a second single instruction to generate a result equivalent to the subtraction of the rounded multiplication result from the negated first operand, whilst producing results which are compliant with the IEEE 754-1985 standard.

摘要翻译： 提供了一种数据处理装置和方法，用于将浮点乘法累加运算应用于第一，第二和第三操作数。 该装置包括用于乘以第二和第三操作数并应用舍入以产生舍入乘法结果的乘法器，以及用于将舍入乘法结果与第一操作数相加以产生最终结果并用于应用舍入以产生舍入的最终结果的加法器 。 此外，提供控制逻辑，其响应于第一单个指令来控制乘法器和加法器，以使由加法器产生的舍入最终结果等效于从第一操作数减去舍入乘法结果。 在优选实施例中，控制逻辑还响应于另一单个指令来控制乘法器和加法器，以使由加法器产生的舍入最终结果等效于从否定的第一操作数的舍入乘法结果的相减。这样 方法，乘法累加逻辑可以被布置为提供快速执行第一单个指令以产生等效于从第一操作数减去舍入乘法结果的结果，或者产生第二单个指令以产生等效于相减 来自否定的第一操作数的舍入乘积，同时产生符合IEEE 754-1985标准的结果。

公开(公告)号：US06189094B1

公开(公告)日：2001-02-13

申请号：US09085752

申请日：1998-05-27

申请人： Christopher Neal Hinds ,  David Vivian Jaggar ,  David Terrence Matheny ,  David James Seal

发明人： Christopher Neal Hinds ,  David Vivian Jaggar ,  David Terrence Matheny ,  David James Seal

IPC分类号： G06F1578

CPC分类号： G06F9/3861 ,  G06F9/30014 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3867

摘要： A floating point unit having a register bank containing a plurality of registers supports vector operations that execute a specified operation a plurality of times upon a sequence of data values form different registers. The register bank is divided into subsets and with the sequence of registers used in a vector operation wrapping within a subset. The subsets comprise disjoint, contiguous ranges of register numbers. The wrapping within ranges allows compact code and efficient to be provided for performing DSP operations, such as FIR filtering and matrix transformations.

摘要翻译： 具有包含多个寄存器的寄存器组的浮点单元支持在数据值序列形成不同寄存器时多次执行指定操作的向量操作。 寄存器组被划分为子集以及在子集中的矢量操作中使用的寄存器序列。 子集包括不相交的寄存器编号的连续范围。 范围内的包装允许紧凑的代码和有效的提供用于执行DSP操作，如FIR滤波和矩阵转换。