公开(公告)号：US07802080B2

公开(公告)日：2010-09-21

申请号：US10807498

申请日：2004-03-24

申请人： David John Butcher ,  Stephen John Hill ,  Hedley James Francis ,  Vladimir Vasekin ,  Andrew Christopher Rose

发明人： David John Butcher ,  Stephen John Hill ,  Hedley James Francis ,  Vladimir Vasekin ,  Andrew Christopher Rose

IPC分类号： G06F9/40 ,  G06F9/44 ,  G06F9/445

CPC分类号： G06F9/3861 ,  G06F9/30174 ,  G06F9/355

摘要： A processor 6 is provided with an instruction decoder 18 which is responsive to memory access instructions to determine whether the base register value being used matches a null value and if such a match occurs then branches to a null value exception handler.

摘要翻译： 处理器6设置有指令解码器18，该指令解码器18响应于存储器访问指令来确定正在使用的基本寄存器值是否与空值匹配，并且如果发生这样的匹配，则分支到空值异常处理程序。

公开(公告)号：US07529889B2

公开(公告)日：2009-05-05

申请号：US11503410

申请日：2006-08-14

申请人： Vladimir Vasekin ,  Stuart David Biles

发明人： Vladimir Vasekin ,  Stuart David Biles

IPC分类号： G06F12/08

CPC分类号： G06F12/0884 ,  G06F2212/1028 ,  Y02D10/13

摘要： A data processing apparatus and method are provided for performing a cache lookup in an energy efficient manner. The data processing apparatus has at least one processing unit for performing operations and a cache having a plurality of cache lines for storing data values for access by that at least one processing unit when performing those operations. The at least one processing unit provides a plurality of sources from which access requests are issued to the cache, and each access request, in addition to specifying an address, further includes a source identifier indicating the source of the access request. A storage element is provided for storing for each source an indication as to whether the last access request from that source resulted in a hit in the cache, and cache line identification logic determines, for each access request, whether that access request is seeking to access the same cache line as the last access request issued by that source. The cache control logic is operable when handling an access request to constrain the lookup procedure to only a subset of the storage blocks within the cache if it is determined that the access request is to the same cache line as the last access request issued by the relevant source, and the storage element indicates that the last access request from that source resulted in a hit in the cache. This yields significant energy savings when accessing the cache.

摘要翻译： 提供了一种以能量效率方式执行高速缓存查找的数据处理装置和方法。 所述数据处理装置具有用于执行操作的至少一个处理单元和具有多个高速缓存行的高速缓存，所述高速缓存行用于在执行所述操作时存储由所述至少一个处理单元访问的数据值。 所述至少一个处理单元提供多个源，从所述多个源向所述高速缓存发出访问请求，并且除了指定地址之外，每个访问请求还包括指示所述访问请求的源的源标识符。 提供存储元件，用于为每个源存储关于来自该源的最后访问请求是否导致高速缓存中的命中的指示，并且高速缓存行标识逻辑针对每个访问请求确定该访问请求是否正在寻求访问 与该源发出的最后访问请求相同的高速缓存行。 如果确定访问请求与由相关的最后访问请求发送到相同的高速缓存行，则处理访问请求以将查找过程限制为仅在缓存内的存储块的子集的情况下，高速缓存控制逻辑可操作 源，并且存储元素指示来自该源的最后访问请求导致高速缓存中的命中。 这在访问缓存时可以节省大量能源。

公开(公告)号：US20080270749A1

公开(公告)日：2008-10-30

申请号：US11790483

申请日：2007-04-25

申请人： Emre Ozer ,  Vladimir Vasekin ,  Stuart David Biles

发明人： Emre Ozer ,  Vladimir Vasekin ,  Stuart David Biles

IPC分类号： G06F15/00

CPC分类号： G06F9/3851 ,  G06F9/3822 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384

摘要： A multi-threaded in-order superscalar processor 2 is described having a fetch stage 8 within which thread interleaving circuitry 36 interleaves instructions taken from different program threads to form an interleaved stream of instructions which is then decoded and subject to issue. Hint generation circuitry 62 within the fetch stage 8 adds hint data to the threads indicating that parallel issue of an associated instruction is permitted with one of more other instructions.

摘要翻译： 描述了具有提取级8的多线程顺序超标量处理器2，线程交织电路36交织来自不同节目线程的指令，以形成交织的指令流，然后解码并发生问题。 提取阶段8内的提示生成电路62向线程添加提示数据，指示相关指令的并行发行被许多其他指令之一允许。

公开(公告)号：US07707390B2

公开(公告)日：2010-04-27

申请号：US11790483

申请日：2007-04-25

申请人： Emre Özer ,  Vladimir Vasekin ,  Stuart David Biles

发明人： Emre Özer ,  Vladimir Vasekin ,  Stuart David Biles

IPC分类号： G06F9/00

CPC分类号： G06F9/3851 ,  G06F9/3822 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384

摘要： A multi-threaded in-order superscalar processor 2 is described having a fetch stage 8 within which thread interleaving circuitry 36 interleaves instructions taken from different program threads to form an interleaved stream of instructions which is then decoded and subject to issue. Hint generation circuitry 62 within the fetch stage 8 adds hint data to the threads indicating that parallel issue of an associated instruction is permitted with one of more other instructions.

摘要翻译： 描述了具有提取级8的多线程顺序超标量处理器2，线程交织电路36交织来自不同节目线程的指令，以形成交织的指令流，然后解码并发生问题。 提取阶段8内的提示生成电路62向线程添加提示数据，指示相关指令的并行发行被许多其他指令之一允许。

公开(公告)号：US20080040592A1

公开(公告)日：2008-02-14

申请号：US11501920

申请日：2006-08-10

申请人： Vladimir Vasekin ,  Stuart David Biles ,  Andrew Christopher Rose ,  Wilco Dijkstra

发明人： Vladimir Vasekin ,  Stuart David Biles ,  Andrew Christopher Rose ,  Wilco Dijkstra

IPC分类号： G06F15/00

CPC分类号： G06F12/0875 ,  G06F9/30058 ,  G06F9/30181 ,  G06F9/3806 ,  G06F12/0862 ,  G06F2212/6028 ,  Y02D10/13

摘要： A data processing system includes an instruction fetching circuit 2, an instruction queue 4 and further processing circuits 6. A branch target cache, which maybe a branch target address cache 8, a branch target instruction cache 10 or both, is used to store branch target addresses or blocks of instructions starting at the branch target respectively. A control circuit 12 is responsive to the contents of the instruction queue 4 when a branch instruction is encountered to determine whether or not storage resources within the branch target cache 8, 10 should be allocated to that branch instruction. Storage resources within the branch target cache 8, 10 will be allocated when the number of program instructions within the instruction queue is below a threshold number and/or the estimated execution time of the program instructions is below a threshold time.

摘要翻译： 数据处理系统包括指令提取电路2，指令队列4和其他处理电路6。 分支目标高速缓存（分支目标地址高速缓存8，分支目标指令高速缓存10或两者）分别用于存储从分支目标开始的分支目标地址或指令块。 当遇到分支指令时，控制电路12响应于指令队列4的内容，以确定分支目标高速缓存8,10中的存储资源是否应被分配给该分支指令。 当指令队列内的程序指令数量低于阈值数量和/或程序指令的估计执行时间低于阈值时间时，将分配分支目标缓存器8,10内的存储资源。

公开(公告)号：US20070288735A1

公开(公告)日：2007-12-13

申请号：US11449858

申请日：2006-06-09

申请人： Vladimir Vasekin ,  Stuart David Biles ,  Yuri Levdik ,  Andrei Kapustin

发明人： Vladimir Vasekin ,  Stuart David Biles ,  Yuri Levdik ,  Andrei Kapustin

IPC分类号： G06F9/00

CPC分类号： G06F9/3851 ,  G06F9/30101 ,  G06F9/3848

摘要： A branch prediction mechanism 16, 18 within a multithreaded processor having hardware scheduling logic 6, 8, 10, 12 uses a shared global history table 18 which is indexed by respective branch history registers 20, 22 for each program thread. Different mappings are used between preceding branch behaviour and the prediction value stored within respective branch history registers 20, 22. These different mappings may be provided by inverters placed into the shift in paths for the branch history registers 20, 22 or by adders 40, 42 or in some other way. The different mappings help to equalise the probability of use of the particular storage locations within the global history table 18 such that the plurality of program threads are not competing excessively for the same storage locations corresponding to the more commonly occurring patterns of preceding branch behaviour.

摘要翻译： 具有硬件调度逻辑6,8,10,12的多线程处理器内的分支预测机制16,18使用共享全局历史表18，该共享全局历史表18由各个分支历史寄存器20,22针对每个程序线索引。 在之前的分支行为与存储在相应分支历史寄存器20,22内的预测值之间使用不同的映射。 这些不同的映射可以由放置在用于分支历史寄存器20,22的路径中的变换器或由加法器40,42或以某种其他方式提供。 不同的映射有助于使全局历史表18中的特定存储位置的使用概率相等，使得多个程序线程对于与先前分支行为的更常见的模式相对应的相同存储位置不会过度竞争。

公开(公告)号：US20070226473A1

公开(公告)日：2007-09-27

申请号：US11592323

申请日：2006-11-03

申请人： Andrei Kapustin ,  Yuri Ledvik ,  Vladimir Vasekin

发明人： Andrei Kapustin ,  Yuri Ledvik ,  Vladimir Vasekin

IPC分类号： G06F9/44

CPC分类号： G06F11/3648

摘要： A data processing system 2 is provided with breakpoint circuitry 28 having breakpoint registers 30 which can specify a variety of different types of breakpoint conditions. These breakpoint conditions include register access breakpoints which are triggered when an access is made to either a general purpose register 8 or a configuration register 22, 24. The breakpoints can also include input/output port access breakpoints which are triggered when an access is made to a predetermined one of a plurality of input/output ports 26 by an appropriate program instruction or in another way.

摘要翻译： 数据处理系统2具有断点电路28，断点电路28具有可指定各种不同类型的断点条件的断点寄存器30。 这些断点条件包括当访问通用寄存器8或配置寄存器22,24时被触发的寄存器访问断点。 断点还可以包括当通过适当的程序指令或以另一种方式对多个输入/输出端口26中的预定的一个进行访问时触发的输入/输出端口访问断点。

公开(公告)号：US07178011B2

公开(公告)日：2007-02-13

申请号：US10765867

申请日：2004-01-29

申请人： David James Seal ,  Vladimir Vasekin

发明人： David James Seal ,  Vladimir Vasekin

IPC分类号： G06F9/40

CPC分类号： G06F9/30072 ,  G06F9/30058 ,  G06F9/30181

摘要： Within a data processing system, prediction instructions are provided which add conditional behaviour to associated program instructions.

摘要翻译： 在数据处理系统中，提供预测指令，其向相关程序指令添加条件行为。

公开(公告)号：US08954715B2

公开(公告)日：2015-02-10

申请号：US13422539

申请日：2012-03-16

申请人： Vladimir Vasekin ,  Andrew Christopher Rose ,  Allan John Skillman ,  Antony John Penton

发明人： Vladimir Vasekin ,  Andrew Christopher Rose ,  Allan John Skillman ,  Antony John Penton

IPC分类号： G06F9/38 ,  G06F11/267

CPC分类号： G06F9/38 ,  G06F9/3851 ,  G06F11/267

摘要： A multithreading processor 4 interleaves program instructions from different program threads to perform fine grained multithreading. Thread performance monitoring circuitry 30 monitors performance parameters of individual program threads to generate performance values. Issue control circuitry 28 reads these performance values to determine which program thread is next selected to be active when a thread switch event occurs. The performance parameters measured may include the proportion of cycles in which a program thread is able to provide a program instruction for execution by the execution circuitry 12 within the processor 4.

摘要翻译： 多线程处理器4交织来自不同程序线程的程序指令，以执行细粒度多线程。 线程性能监视电路30监视各个程序线程的性能参数以产生性能值。 问题控制电路28读取这些性能值，以确定当线程切换事件发生时下一个选择哪个程序线程处于活动状态。 测量的性能参数可以包括程序线程能够提供用于由处理器4内的执行电路12执行的程序指令的循环的比例。

公开(公告)号：US20120260070A1

公开(公告)日：2012-10-11

申请号：US13422539

申请日：2012-03-16

申请人： Vladimir VASEKIN ,  Andrew Christopher Rose ,  Allan John Skillman ,  Antony John Penton

发明人： Vladimir VASEKIN ,  Andrew Christopher Rose ,  Allan John Skillman ,  Antony John Penton

IPC分类号： G06F9/30

CPC分类号： G06F9/38 ,  G06F9/3851 ,  G06F11/267

摘要： A multithreading processor 4 interleaves program instructions from different program threads to perform fine grained multithreading. Thread performance monitoring circuitry 30 monitors performance parameters of individual program threads to generate performance values. Issue control circuitry 28 reads these performance values to determine which program thread is next selected to be active when a thread switch event occurs. The performance parameters measured may include the proportion of cycles in which a program thread is able to provide a program instruction for execution by the execution circuitry 12 within the processor 4.

摘要翻译： 多线程处理器4交织来自不同程序线程的程序指令，以执行细粒度多线程。 线程性能监视电路30监视各个程序线程的性能参数以产生性能值。 问题控制电路28读取这些性能值，以确定当线程切换事件发生时下一个选择哪个程序线程处于活动状态。 测量的性能参数可以包括程序线程能够提供用于由处理器4内的执行电路12执行的程序指令的循环的比例。