公开(公告)号：US08356119B2

公开(公告)日：2013-01-15

申请号：US12662625

申请日：2010-04-26

申请人： Mittu Xavier Kocherry ,  Antony John Penton ,  Simon John Craske

发明人： Mittu Xavier Kocherry ,  Antony John Penton ,  Simon John Craske

IPC分类号： G06F3/00

CPC分类号： G06F13/102 ,  G06F13/385

摘要： A data processing apparatus is disclosed that is configured to communicate via an output port with a plurality of devices and to issue a stream of transaction requests to the output port, the stream of transaction requests comprising at least some device transaction requests destined for the plurality of devices. Device transactions are transactions that may affect each other and therefore should be completed in an order in which they are received at the output port in. The output port is configured to output the received transaction requests as a single serial stream of transaction requests. The data processing apparatus comprises: a destination device detector for monitoring the device transaction requests and for determining which of the plurality of devices each of the device transaction requests are destined for; the output port comprises ordering circuitry configured to treat the plurality of devices as at least two subsets of devices, at least one of the subsets comprising at least two devices; the ordering circuitry being configured to receive the stream of transaction requests and to classify each of the device transaction requests into one of the at least two subsets in response to determination of a destination device by said destination device detector, and to maintain said order that said device transaction requests within each subset are received in, such that device transaction requests within each subset are output by the output port and executed by their respective destination devices in the received order, while device transaction requests within different subsets may be output in an order that is different to the received order.

摘要翻译： 公开了一种数据处理装置，其被配置为经由输出端口与多个设备进行通信并且向所述输出端口发出事务请求流，所述事务请求流包括至少一些目的地为所述多个设备的事务请求 设备。 设备事务是可能相互影响的事务，因此应该按照在输出端口处接收到的顺序完成。输出端口被配置为将接收到的事务请求作为单个串行事务请求流输出。 数据处理装置包括：目的地设备检测器，用于监视设备事务请求并确定设备交易请求中的每一个设备中的哪一个设备; 所述输出端口包括被配置为将所述多个设备视为至少两个设备子集的订购电路，所述子集中的至少一个包括至少两个设备; 所述订购电路被配置为响应于所述目的地设备检测器对目的地设备的确定而接收所述事务请求流并将所述设备事务请求中的每一个分类为所述至少两个子集中的一个，并且保持所述 每个子集内的设备事务请求被接收，使得每个子集内的设备事务请求由输出端口输出并由其各自的目的地设备以接收到的顺序执行，而不同子集内的设备事务请求可以以 与收到的订单不同。

公开(公告)号：US20110264827A1

公开(公告)日：2011-10-27

申请号：US12662625

申请日：2010-04-26

申请人： Mittu Xavier Kocherry ,  Antony John Penton ,  Simon John Craske

发明人： Mittu Xavier Kocherry ,  Antony John Penton ,  Simon John Craske

IPC分类号： G06F3/00

CPC分类号： G06F13/102 ,  G06F13/385

摘要： A data processing apparatus is disclosed that is configured to communicate via an output port with a plurality of devices and to issue a stream of transaction requests to the output port, the stream of transaction requests comprising at least some device transaction requests destined for the plurality of devices. Device transactions are transactions that may affect each other and therefore should be completed in an order in which they are received at the output port in. The output port is configured to output the received transaction requests as a single serial stream of transaction requests. The data processing apparatus comprises: a destination device detector for monitoring the device transaction requests and for determining which of the plurality of devices each of the device transaction requests are destined for; the output port comprises ordering circuitry configured to treat the plurality of devices as at least two subsets of devices, at least one of the subsets comprising at least two devices; the ordering circuitry being configured to receive the stream of transaction requests and to classify each of the device transaction requests into one of the at least two subsets in response to determination of a destination device by said destination device detector, and to maintain said order that said device transaction requests within each subset are received in, such that device transaction requests within each subset are output by the output port and executed by their respective destination devices in the received order, while device transaction requests within different subsets may be output in an order that is different to the received order.

摘要翻译： 公开了一种数据处理装置，其被配置为经由输出端口与多个设备进行通信并且向所述输出端口发出事务请求流，所述事务请求流包括至少一些目的地为所述多个设备的事务请求 设备。 设备事务是可能相互影响的事务，因此应该按照在输出端口处接收到的顺序完成。输出端口被配置为将接收到的事务请求作为单个串行事务请求流输出。 数据处理装置包括：目的地设备检测器，用于监视设备事务请求并确定设备交易请求中的每一个设备中的哪一个设备; 所述输出端口包括被配置为将所述多个设备视为至少两个设备子集的订购电路，所述子集中的至少一个包括至少两个设备; 所述订购电路被配置为响应于所述目的地设备检测器对目的地设备的确定而接收所述事务请求流并将所述设备事务请求中的每一个分类为所述至少两个子集中的一个，并且保持所述 每个子集内的设备事务请求被接收，使得每个子集内的设备事务请求由输出端口输出并由其各自的目的地设备以接收到的顺序执行，而不同子集内的设备事务请求可以以 与收到的订单不同。

公开(公告)号：US20110191543A1

公开(公告)日：2011-08-04

申请号：US12656538

申请日：2010-02-02

申请人： Simon John Craske ,  Antony John Penton ,  Loic Pierron ,  Andrew Christopher Rose

发明人： Simon John Craske ,  Antony John Penton ,  Loic Pierron ,  Andrew Christopher Rose

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0831 ,  G06F12/0804 ,  G06F2212/1024 ,  Y02D10/13

摘要： An apparatus for storing data that is being processed is disclosed. The apparatus comprises: a cache associated with a processor and for storing a local copy of data items stored in a memory for use by the processor, monitoring circuitry associated with the cache for monitoring write transaction requests to the memory initiated by a further device, the further device being configured not to store data in the cache. The monitoring circuitry is responsive to detecting a write transaction request to write a data item, a local copy of which is stored in the cache, to block a write acknowledge signal transmitted from the memory to the further device indicating the write has completed and to invalidate the stored local copy in the cache and on completion of the invalidation to send the write acknowledge signal to the further device.

摘要翻译： 公开了一种用于存储正在处理的数据的装置。 该装置包括：与处理器相关联的用于存储在存储器中用于由处理器使用的数据项的本地副本的高速缓存，用于监控与高速缓存相关联的监视电路，用于监视由另一设备发起的存储器的写事务请求， 进一步的设备被配置为不将数据存储在高速缓存中。 监视电路响应于检测到写入事务请求来写入其本地副本存储在高速缓存中的数据项，以阻止从存储器发送到指示写入已完成的另一设备的写入确认信号，并使其无效 存储的本地副本在缓存中并完成无效，以将写入确认信号发送到另一个设备。

公开(公告)号：US20110179309A1

公开(公告)日：2011-07-21

申请号：US12656248

申请日：2010-01-21

申请人： Chiloda Ashan Senerath Pathirane ,  Antony John Penton

发明人： Chiloda Ashan Senerath Pathirane ,  Antony John Penton

IPC分类号： G06F11/07

CPC分类号： G06F11/3648

摘要： A data processing system 2 is provided with multiple processors 4, 6 which can operate in either a split-mode in which each processor executes its own program flow or a locked-mode in which the processors execute the same program flow. Debug circuitry 8, 10 is associated with each of the processors. In an emulation-locked mode of operation, one of the processors 4 is active and its respective debug circuitry 8 is active to update the debug state data so as to debug the locked mode code. At the same time, the second processor 6 is held inactive and its state is maintained as well as the debug state data of the debug circuitry 10 within that inactive processor. This maintains the debug state data of the processor 6 across entry and exit to the locked mode of operation.

摘要翻译： 数据处理系统2具有多个处理器4,6，它们可以以每个处理器执行其自己的程序流的分离模式或处理器执行相同程序流程的锁定模式操作。 调试电路8,10与每个处理器相关联。 在仿真锁定操作模式中，处理器4之一是有效的，并且其相应的调试电路8有效以更新调试状态数据，以便调试锁定模式代码。 同时，第二处理器6保持不活动，并且其状态以及该非活动处理器内的调试电路10的调试状态数据被保持。 这保持处理器6的调试状态数据进入和退出到锁定的操作模式。

公开(公告)号：US20110179255A1

公开(公告)日：2011-07-21

申请号：US12656246

申请日：2010-01-21

申请人： Chiloda Ashan Senerath Pathirane ,  Antony John Penton ,  Andrew Christopher Rose

发明人： Chiloda Ashan Senerath Pathirane ,  Antony John Penton ,  Andrew Christopher Rose

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F12/08

CPC分类号： G06F11/0793 ,  G06F1/24

摘要： A processor 4 is provided with reset circuitry 48 which generates a reset signal to reset a plurality of state parameters. Partial reset circuitry 50 is additionally provided to reset a proper subset of this plurality of state parameters. The reset circuitry triggers a redirection of program flow. The partial reset circuitry permits a continuation of program flow. The partial reset circuitry may be used to place processors into a known state with a low latency before switching from a split mode of operation into a locked mode of operation.

摘要翻译： 处理器4设置有复位电路48，其产生复位信号以复位多个状态参数。 另外提供部分复位电路50以复位该多个状态参数的正确子集。 复位电路触发程序流的重定向。 部分复位电路允许继续程序流程。 部分复位电路可以用于在从分离操作模式切换到锁定操作模式之前将处理器置于具有低延迟的已知状态。

公开(公告)号：US20110093686A1

公开(公告)日：2011-04-21

申请号：US12923357

申请日：2010-09-16

申请人： Antony John Penton ,  Simon Axford

发明人： Antony John Penton ,  Simon Axford

IPC分类号： G06F12/16 ,  G06F9/302 ,  G06F9/38

CPC分类号： G06F9/462 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/3834

摘要： In a data processing apparatus 1 having registers 6, when a state saving trigger event occurs while a result value of a data processing operation is still to be written to a destination register then saving and restoring control circuitry 12 selects a state saving sequence defining a temporal order for saving register values to a backup data store 10. The sequence is selected to provide the destination register with a position within the sequence corresponding to a time after the result value has been written to the destination register. The register values are then saved to the backup data store 10 in the order of the selected state saving sequence. A similar technique can be used when a state restoring trigger event triggers loading of the data values from the backup data store 10 to the registers 6.

摘要翻译： 在具有寄存器6的数据处理装置1中，当数据处理操作的结果值仍然被写入目的地寄存器时发生状态保存触发事件时，保存和恢复控制电路12选择定义时间的状态保存序列 命令用于将寄存器值保存到备份数据存储器10.该序列被选择以向目标寄存器提供与结果值已被写入目的地寄存器之后的时间对应的序列内的位置。 然后，寄存器值按所选择的状态保存顺序的顺序被保存到备份数据存储器10中。 当状态恢复触发事件触发将数据值从备份数据存储器10加载到寄存器6时，可以使用类似的技术。

公开(公告)号：US08621336B2

公开(公告)日：2013-12-31

申请号：US12222085

申请日：2008-08-01

申请人： Simon John Craske ,  Andrew Christopher Rose ,  Paul Stanley Hughes ,  Antony John Penton ,  Richard York ,  Simon Andrew Ford ,  Stuart David Biles ,  Alex James Waugh

发明人： Simon John Craske ,  Andrew Christopher Rose ,  Paul Stanley Hughes ,  Antony John Penton ,  Richard York ,  Simon Andrew Ford ,  Stuart David Biles ,  Alex James Waugh

IPC分类号： G06F11/00

CPC分类号： G06F11/1064

摘要： A data processing apparatus is provided comprising processing circuitry for performing data processing operations, a set associative storage device for storing data values for access by the processing circuitry when performing data processing operations, error detection circuitry for performing, for each access to the storage device, an error detection operation on the data value accessed, and maintenance circuitry associated with the storage device for performing one or more maintenance operations. The processing circuitry is arranged to issue an error detection maintenance request to the maintenance circuitry specifying at least one specific physical location within the storage device, and the maintenance circuitry is responsive to the error detection maintenance request to perform at least one dummy access to the at least one specific physical location within the storage device and to provide the processing circuitry with error status information derived from the error detection operation performed by the error detection circuitry in respect of said at least one dummy access.

公开(公告)号：US08108730B2

公开(公告)日：2012-01-31

申请号：US12656248

申请日：2010-01-21

申请人： Chiloda Ashan Senerath Pathirane ,  Antony John Penton

发明人： Chiloda Ashan Senerath Pathirane ,  Antony John Penton

IPC分类号： G06F11/00

CPC分类号： G06F11/3648

摘要： A data processing system 2 is provided with multiple processors 4, 6 which can operate in either a split-mode in which each processor executes its own program flow or a locked-mode in which the processors execute the same program flow. Debug circuitry 8, 10 is associated with each of the processors. In an emulation-locked mode of operation, one of the processors 4 is active and its respective debug circuitry 8 is active to update the debug state data so as to debug the locked mode code. At the same time, the second processor 6 is held inactive and its state is maintained as well as the debug state data of the debug circuitry 10 within that inactive processor. This maintains the debug state data of the processor 6 across entry and exit to the locked mode of operation.

摘要翻译： 数据处理系统2设置有多个处理器4,6，其可以以每个处理器执行其自己的程序流的分离模式或处理器执行相同的程序流程的锁定模式操作。 调试电路8,10与每个处理器相关联。 在仿真锁定操作模式中，处理器4之一是有效的，并且其相应的调试电路8有效以更新调试状态数据，以便调试锁定模式代码。 同时，第二处理器6保持不活动，并且其状态以及该非活动处理器内的调试电路10的调试状态数据被保持。 这保持处理器6的调试状态数据进入和退出到锁定的操作模式。

公开(公告)号：US08051323B2

公开(公告)日：2011-11-01

申请号：US12656247

申请日：2010-01-21

申请人： Chiloda Ashan Senerath Pathirane ,  Antony John Penton

发明人： Chiloda Ashan Senerath Pathirane ,  Antony John Penton

IPC分类号： G06F11/00

CPC分类号： G06F11/0751 ,  G06F9/30189 ,  G06F9/3851 ,  G06F11/0724 ,  G06F11/073

摘要： A multiple-processor system 2 is provided where each processor 4-0, 4-1 can be dynamically switched between running in a locked mode where one processor 4-1 checks the operation of the other processor 4-0 and a split mode where each processor 4-0, 4-1 operates independently. Multiple auxiliary circuits 8-0, 8-1 provide auxiliary functions for the plurality of processors 4-0, 4-1. In the split mode, each auxiliary circuit 8-0, 8-1 separately provides auxiliary functions for a corresponding one of the processors 4-0, 4-1. To ensure coherency when each processor 4-0, 4-1 executes a common set of processing operations, in the locked mode a shared one of the auxiliary circuits 8-0 provides auxiliary functions for all of the processors 4-0, 4-1.

摘要翻译： 提供了多处理器系统2，其中每个处理器4-0,4-1可以在以一个处理器4-1检查其他处理器4-0的操作的锁定模式和分别模式之间动态切换 处理器4-0，4-1独立运行。 多个辅助电路8-0,8-1为多个处理器4-0,4-1提供辅助功能。 在分离模式中，每个辅助电路8-0,8-1分别为处理器4-0,4-1中相应的一个提供辅助功能。 为了确保当每个处理器4-0,4-1执行一组共同的处理操作时的一致性，在锁定模式中，辅助电路8-0中的共享一个为所有处理器4-0,4-1提供辅助功能 。

公开(公告)号：US20110103400A1

公开(公告)日：2011-05-05

申请号：US12588960

申请日：2009-11-03

申请人： Martinus Cornelis Wezelenburg ,  Antony John Penton ,  Ken Yi Wong

发明人： Martinus Cornelis Wezelenburg ,  Antony John Penton ,  Ken Yi Wong

IPC分类号： H04J3/24

CPC分类号： H04L1/0043 ,  H03M13/19 ,  H03M13/2912 ,  H03M13/2915 ,  H03M13/6502 ,  H03M13/6561 ,  H04L1/0052 ,  H04L1/0057

摘要： An encoder for generating check data to accompaning payload data uses parallel lane encoders 18 each using a common encoder matrix. Mask circuitry 22 applies mask values to the lane check data generated by the lane encoders 18. The mask circuitry 22 generates check data for the K-bits of payload data. The mask values applied by the mask circuitry 22 may be selected so as to bring about a re-ordering of the M-bit words.

摘要翻译： 用于产生用于附带有效载荷数据的检查数据的编码器使用并行通道编码器18，每个编码器使用公共编码器矩阵。 掩模电路22将掩模值应用于由通道编码器18产生的通道检查数据。掩模电路22产生有效载荷数据的K位的检查数据。 可以选择由掩模电路22施加的掩码值，以便引起M位字的重新排序。