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公开(公告)号：US6002881A
公开(公告)日：1999-12-14
申请号：US932053
申请日：1997-09-17
CPC分类号： G06F9/3552 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/325 , G06F9/355 , G06F9/384 , G06F9/3877 , G06F9/3879
摘要： A digital signal processing system comprising a central processing unit core 2, a memory 8 and a coprocessor 4 operates using coprocessor memory access instructions (e.g. LDC, STC). The addressing mode information within these coprocessor memory access instructions (P, U, W, Offset) not only controls the addressing mode used by the central processing unit core 2 but is also used by the coprocessor 4 to determine the number of data words in the transfer being specified such that the coprocessor 4 can terminate the transfer at the appropriate time. Knowledge in advance of the number of words in a transfer is also advantageous in some bus systems, such as those that can be used with synchronous DRAM. The Offset field within the instruction may be used to specify changes to be made in the value provided by the central processing unit core 2 upon execution of a particular instruction and also to specify the number of words in the transfer. This arrangement is well suited to working through a regular array of data such as in digital signal processing operations. If the Offset field is not being used, then the number of words to be transferred may default to 1.
摘要翻译： 包括中央处理单元核心2，存储器8和协处理器4的数字信号处理系统使用协处理器存储器访问指令（例如LDC，STC）进行操作。 这些协处理器存储器访问指令（P，U，W，偏移）内的寻址模式信息不仅控制中央处理单元核心2所使用的寻址模式，而且还由协处理器4使用来确定数据字的数量 传输被指定为使得协处理器4可以在适当的时间终止转移。 在一些总线系统中，诸如可以与同步DRAM一起使用的那些总线系统中的转移数量之前的知识也是有利的。 指令内的偏移字段可以用于指定在执行特定指令时由中央处理单元核心2提供的值进行改变，并且还指定转移中的字数。 这种布置非常适合通过数字信号处理操作中的常规数据阵列进行工作。 如果未使用偏移字段，则要传输的字数可能默认为1。
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公开(公告)号：US06999985B2
公开(公告)日：2006-02-14
申请号：US09941790
申请日：2001-08-30
IPC分类号： G06F7/38
CPC分类号： G06F7/505 , G06F7/49931 , G06F9/30014 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F2207/3828
摘要： A data processing system is provided with an instruction (ADD8TO16) that unpacks non-adjacent portions of a data word using sign or zero extension and combines this with a single-instruction-multiple-data type arithmetic operation, such as an add, performed in response to the same instruction. The instruction is well suited to use within systems having a data path (2) including a shifting circuit (6) upstream of an arithmetic circuit (8).
摘要翻译： 数据处理系统提供有使用符号或零扩展来解开数据字的非相邻部分的指令（ADD8TO16），并将其与单指令多数据类型算术运算（例如，在 对同一指令的回应。 该指令非常适合于在具有在运算电路（8）上游的移位电路（6）的数据路径（2）的系统内使用。
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3.发明授权Data processing apparatus and method for moving data between registers and memory in response to an access instruction having an alignment specifier identifying an alignment to be associated with a start address 有权数据处理装置和方法，用于响应于具有标识与开始地址相关联的对准的对准指定符的访问指令来在寄存器和存储器之间移动数据公开(公告)号：US07210023B2
公开(公告)日：2007-04-24
申请号：US10889470
申请日：2004-07-13
IPC分类号： G06F7/00
CPC分类号： G06F9/3004 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/30116 , G06F9/30138 , G06F9/30181 , G06F9/3816
摘要： The present invention provides a data processing apparatus and method for performing aligned access operations. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements, and a processor operable to perform a data processing operation on one or more data elements accessed in at least one of the registers. Further, access logic is provided which is operable in response to an access instruction to perform an access operation in order to move a number of data elements between specified registers and a portion of a memory, the portion having a start address specified by the access instruction. Further, the access instruction has an alignment specifier associated therewith which is settable either to a first value or one of a plurality of second values. The first value indicates that the start address is to be treated as byte aligned, and each of the second values indicates a different predetermined alignment that the start address is to be treated as conforming to. The access logic is then operable to adapt the access operation in dependence on the value of alignment specifier. This provides significantly improved flexibility in the performance of access operations.
摘要翻译： 本发明提供一种用于执行对准访问操作的数据处理装置和方法。 数据处理装置包括具有可操作以存储数据元素的多个寄存器的寄存器数据存储器，以及可操作以对在至少一个寄存器中访问的一个或多个数据元素执行数据处理操作的处理器。 此外，提供访问逻辑，其可响应于访问指令而操作以执行访问操作，以便在指定的寄存器和存储器的一部分之间移动多个数据元素，该部分具有由访问指令指定的起始地址 。 此外，访问指令具有与其相关联的对齐说明符，其可设置为第一值或多个第二值中的一个。 第一个值表示起始地址被视为字节对齐，并且每个第二个值指示起始地址被视为符合的不同的预定对齐方式。 然后，访问逻辑可操作以根据对准说明符的值来适应访问操作。 这样可以显着提高访问操作性能的灵活性。
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公开(公告)号：US06598061B1
公开(公告)日：2003-07-22
申请号：US09594081
申请日：2000-06-15
IPC分类号： G06F772
CPC分类号： G06F7/728
摘要： The present invention provides a system, method and computer program for performing a modular multiplication a*b*2−N modulo n, where a, b and n are N-bit integers. The system comprises a multiplier for multiplying a Y-bit number by a Z-bit number, and partitioning logic for partitioning the integer a into a plurality of first sections, each first section being of a size which is a multiple of Y, and for partitioning the integer b into a plurality of second sections, each second section being of a size which is a multiple of Z. A multiplication unit is then provided to apply operations to control the multiplier to perform a sequence of multiplications to multiply one of said first sections by one of said second sections in order to generate a number of output operands for use in subsequent operations performed by the multiplication unit. A controller is used to sequentially input one of said first sections and one of said second sections into the multiplication unit along with predetermined ones of said output operands from preceding operations performed by the multiplication unit, until each first section has been multiplied by each second section. By this approach, a multiplication unit can be provided which is of a fixed size, irrespective of the size of the input integers, a b and n. This alleviates the requirements for increasingly larger fast storage, the size of the fast storage being dependent not on the ultimate size of the N-bit integers, but rather on the predetermined size of the sections into which those integers are partitioned.
摘要翻译： 本发明提供了一种用于执行乘法a * b * 2-N模n的系统，方法和计算机程序，其中a，b和n是N位整数。 该系统包括用于将Y比特数乘以Z比特数的乘法器和用于将整数a分割成多个第一部分的分割逻辑，每个第一部分的大小是Y的倍数，并且对于 将整数b分割成多个第二部分，每个第二部分的尺寸是Z的倍数。然后提供乘法单元以施加操作以控制乘数以执行乘法序列，以乘以所述第一 以产生用于由乘法单元执行的后续操作中的多个输出操作数。 控制器用于将所述第一部分中的一个和所述第二部分中的一个顺序输入到乘法单元中，以及由乘法单元执行的先前操作的所述输出操作数中的预定的一个，直到每个第一部分已经被每个第二部分 。 通过该方法，可以提供具有固定大小的乘法单元，而与输入整数a b和n的大小无关。 这减轻了越来越大的快速存储的要求，快速存储的大小不取决于N位整数的最终大小，而是取决于这些整数被分割成的区段的预定大小。
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公开(公告)号：US08954711B2
公开(公告)日：2015-02-10
申请号：US13361229
申请日：2012-01-30
CPC分类号： G06F9/3557 , G06F9/30007 , G06F9/30112 , G06F9/30167 , G06F9/342 , G06F9/345 , G06F2212/657
摘要： A data processing apparatus is provided comprising processing circuitry and an instruction decoder responsive to program instructions to control processing circuitry to perform the data processing. The instruction decoder is responsive to an address calculating instruction to perform an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value such that a full address specifying a memory location of an information entity is calculable from said partial address result using at least one supplementary program instruction. The partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction. A corresponding data processing method, virtual machine and computer program product are also provided.
摘要翻译： 提供了一种数据处理装置，其包括响应于程序指令的处理电路和指令解码器，以控制处理电路执行数据处理。 指令解码器响应于地址计算指令来执行地址计算操作，用于从非固定参考地址和部分偏移值计算部分地址结果，使得可以从...计算指定信息实体的存储位置的完整地址 所述部分地址结果使用至少一个补充程序指令。 部分偏移值具有大于或等于所述指令大小的位宽，并且被编码在所述地址计算指令的至少一个部分偏移字段内。 还提供了相应的数据处理方法，虚拟机和计算机程序产品。
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公开(公告)号：US20120131312A1
公开(公告)日：2012-05-24
申请号：US13137948
申请日：2011-09-22
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F7/764 , G06F7/768 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/3887
摘要： A data processing apparatus 2 comprises a processing circuit 4 and instruction decoder 6. A bitfield manipulation instruction controls the processing apparatus 2 to generate at least one result data element from corresponding first and second source data elements src1, src2. Each result data element includes a portion corresponding to a bitfield bf of the corresponding first source data element src1. Bits of the result data element that are more significant than the inserted bitfield bf have a prefix value p that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element src2, and a third prefix value corresponding to a sign extension of the bitfield bf of the first source data element src1.
摘要翻译： 数据处理装置2包括处理电路4和指令解码器6.位
域操作指令控制处理装置2，从对应的第一和第二源数据元素src1，src2生成至少一个结果数据元素。 每个结果数据元素包括对应于相应的第一源数据元素src1的位字段bf的部分。 比插入的位字段bf更重要的结果数据元素的位具有基于由指令指定的控制值被选择的前缀值p作为具有零值的第一前缀值，第二前缀值 具有相应的第二源数据元素src2的一部分的值，以及与第一源数据元素src1的位域bf的符号扩展对应的第三前缀值。-
公开(公告)号：US07370180B2
公开(公告)日：2008-05-06
申请号：US10793954
申请日：2004-03-08
CPC分类号： G06F5/00 , G06F7/764 , G06F9/30029 , G06F9/30032
摘要： A method of controlling data processing logic which causes a data value to be rotated by a number of bits in order to generate a rotated data value; a number of least significant bits of the rotated data value are masked with other bits of said rotated data value not being masked in order to generate a masked rotated data value; a selected bit of said rotated data value are masked with other bits of said rotated data value not being masked in order to generate a bit preset rotated data value; and said sign-extended bit field extracted data value to be generated by subtracting said masked rotated data value from said bit preset data value or said zero-extended bit field extracted data value to be generated by performing a logical exclusive-OR operation with the masked rotated data value and said bit preset data value.
摘要翻译： 一种控制数据处理逻辑的方法，其使得数据值被旋转多个位以便产生旋转的数据值; 旋转的数据值的多个最低有效位被掩蔽，所述旋转数据值的其他位未被屏蔽，以便产生被屏蔽的旋转数据值; 所述旋转数据值的选择位被掩蔽，所述旋转数据值的其他位未被屏蔽，以便产生位预设旋转数据值; 并且通过从所述位预设数据值或所述零扩展位字段提取的数据值中减去所述被屏蔽的旋转数据值来产生所述符号扩展位字段提取的数据值，以通过执行与被掩蔽的逻辑异或运算 旋转数据值和所述位预置数据值。
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8.发明授权Apparatus and method for processing data having a mixed vector/scalar register file 失效用于处理具有混合向量/标量寄存器文件的数据的装置和方法公开(公告)号：US06282634B1
公开(公告)日：2001-08-28
申请号：US09084304
申请日：1998-05-27
IPC分类号： G06F930
CPC分类号： G06F9/30098 , G06F7/483 , G06F7/49957 , G06F7/5443 , G06F9/30087 , G06F9/30112 , G06F9/30138 , G06F9/30145 , G06F9/3016 , G06F9/345 , G06F9/3455 , G06F9/3838 , G06F9/3877
摘要： A floating point unit is provided with a register bank comprising 32 registers that may be used as either vector registers of scalar registers. A data processing instruction includes at least one register specifying field pointing to a register containing a data value to be used in that operation. An increase in the instruction bit space available to encode more opcodes or to allow for more registers is provided by encoding whether a register is to be treated as a vector or a scalar within the register field itself. Further, the register field for one register of the instruction may encode whether another register is a vector or a scalar. The registers can be initially accessed using the values within the register fields of the instruction independently of the opcode allowing for easier decode.
摘要翻译： 浮点单元设有一个寄存器组，包括32个寄存器，可用作标量寄存器的向量寄存器。 数据处理指令包括指向包含要在该操作中使用的数据值的寄存器的至少一个寄存器指定字段。 通过编码寄存器是否被视为寄存器字段本身中的向量或标量，可以提供可用于编码更多操作码或允许更多寄存器的指令位空间的增加。 此外，指令的一个寄存器的寄存器字段可以编码另一寄存器是矢量还是标量。 可以使用独立于操作码的指令的寄存器字段内的值来初始访问寄存器，从而更容易解码。
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公开(公告)号：US6148314A
公开(公告)日：2000-11-14
申请号：US143614
申请日：1998-08-28
CPC分类号： G06F7/485 , G06F7/5443 , G06F7/49947
摘要： A floating point unit is described that performs addition operations. An adder 16 within the floating point unit receives a first input and a second input to generate a sum. This sum is subject to subsequent normalization by a normalizer 60 and rounding by an incrementer 64. If an operation is performed that is immediately followed by an addition operation using the result of the preceding operation, then the normalized but unrounded sum is fed back to the adder 16 together with an indication of its rounding requirement. This rounding requirement can be performed by the adder 16 in parallel with the execution of the following addition by using the carry-in bit of the adder 16 to apply any increment required to rounding of the preceding result.
摘要翻译： 描述了执行附加操作的浮点单元。 浮点单元内的加法器16接收第一输入和第二输入以产生和。 该总和经归一化器60随后归一化，并由加法器64进行舍入。如果使用前一操作的结果紧接着进行加法运算的操作，则将归一化但未被包围的和反馈到 加法器16以及其舍入要求的指示。 该加法器16可以通过使用加法器16的进位位并行执行后续加法来执行舍入要求，以应用对前一结果进行舍入所需的任何增量。
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10.发明授权
公开(公告)号：US06035383A
公开(公告)日：2000-03-07
申请号：US962832
申请日：1997-11-03
申请人： David James Seal
发明人： David James Seal
CPC分类号： G06F9/34 , G06F9/383 , G06F9/3832 , G06F9/3834 , G06F9/3861
摘要： A data processing system having a processor core 4, a memory management unit 6 and a cache memory 8 uses the memory management unit 6 to produce a confirm signal C that indicates that a memory access request will be processed no further, i.e. the outcome is fully determined. The next memory access request is initiated prior to this confirm signal C being available and accordingly if the confirm signal C indicates a result different to that predicted, then a stall of the system is required until the non-confirmed memory access request can be dealt with. A result prediction unit 14 is responsive to one or more variable signals characterising the memory access request and serves to produce a result prediction signal RP indicating in which of a plurality of ways said memory access requested will complete, which is available before the confirm signal C, and upon which an appropriate predicted next memory access request may be prepared for use if the confirm signal C indicates that the memory access request will be processed no further. In this way, the performance impact of late indication of partial processing can be reduced, particularly in the case of common and relatively easy to predict circumstances such as cache storage line wrap.
摘要翻译： 具有处理器核心4，存储器管理单元6和高速缓冲存储器8的数据处理系统使用存储器管理单元6产生指示不再进一步处理存储器访问请求的确认信号C，即结果完全 决心。 在该确认信号C可用之前启动下一个存储器访问请求，因此如果确认信号C指示与预测的结果不同的结果，则需要系统的停顿，直到可以处理未确认的存储器访问请求 。 结果预测单元14响应表征存储器访问请求的一个或多个可变信号，并且用于产生结果预测信号RP，该结果预测信号RP指示所请求的存储器访问的多个方式中的哪一个将在完成确认信号C之前可用 并且如果确认信号C指示将不再进一步处理存储器访问请求，则可以准备适当的预测下一个存储器访问请求以供使用。 以这种方式，可以减少部分处理的延迟指示的性能影响，特别是在普通且相对容易预测的情况下，例如高速缓存存储线包装。
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