公开(公告)号：US20180006048A1

公开(公告)日：2018-01-04

申请号：US15691136

申请日：2017-08-30

申请人： Renesas Electronics Corporation

发明人： Keisuke TSUKAMOTO ,  Tatsuyoshi MIHARA

IPC分类号： H01L27/11531 ,  H01L21/28 ,  H01L21/283 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/265 ,  H01L29/66 ,  H01L29/49 ,  H01L29/45 ,  H01L29/423 ,  H01L27/11573 ,  H01L27/11568 ,  H01L27/11563 ,  H01L27/11521 ,  H01L21/324 ,  H01L21/3213 ,  H01L21/3205 ,  H01L21/311 ,  H01L29/788 ,  H01L29/51

CPC分类号： H01L27/11531 ,  H01L21/265 ,  H01L21/28202 ,  H01L21/28282 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/32053 ,  H01L21/32133 ,  H01L21/324 ,  H01L27/11521 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7881 ,  Y10S438/926

摘要： A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n+-type semiconductor regions for a source or a drain of MISFET are formed in the peripheral circuit region. Then, a metal silicide layer is formed over the n+-type semiconductor regions but the metal silicide layer is not formed over the control gate electrode, the memory gate electrode, and the gate electrode. Subsequently, the gate electrode is removed and replaced with the gate electrode for MISFET, Then, after removing the gate electrode and replacing it with a gate electrode for MISFET, a metal silicide layer is formed over the memory gate electrode and the control gate electrode.