公开(公告)号：US20160190145A1

公开(公告)日：2016-06-30

申请号：US14972260

申请日：2015-12-17

Applicant: Renesas Electronics Corporation

Inventor： Keiichi MAEKAWA ,  Shoji YOSHIDA ,  Takashi TAKEUCHI ,  Hiroshi YANAGITA

IPC: H01L27/112

CPC classification number: H01L27/11206 ,  G11C17/12 ,  G11C17/16 ,  H01L23/5252

Abstract: A semiconductor device includes an SOI substrate and an anti-fuse element formed on the SOI substrate. The SOI substrate has a p type well region formed on a main surface side of a support substrate and an SOI layer formed on the p type well region via a BOX layer. The anti-fuse element has a gate electrode formed on the SOI layer via agate insulating film. The anti-fuse element constitutes a storage element, and a first potential is applied to the gate electrode and a second potential of the same polarity as the first potential is applied to the p type well region in a write operation of the storage element.

Abstract translation: 半导体器件包括形成在SOI衬底上的SOI衬底和抗熔丝元件。 SOI衬底具有通过BOX层形成在支撑衬底的主表面侧的p型阱区和在p型阱区上形成的SOI层。 反熔丝元件具有通过玛瑙绝缘膜在SOI层上形成的栅电极。 反熔丝元件构成存储元件，并且在存储元件的写入操作中，向栅电极施加第一电位，并将与第一电位相同极性的第二电位施加到p型阱区。

公开(公告)号：US20250022924A1

公开(公告)日：2025-01-16

申请号：US18766799

申请日：2024-07-09

Applicant: Renesas Electronics Corporation

Inventor： Keiichi MAEKAWA

IPC: H01L29/40 ,  H01L29/423

Abstract: A field plate electrode FP and a gate electrode GE are formed inside a plurality of trenches TR1. An outer peripheral trench TR2 surrounds the plurality of trenches TR1 in plan view. A field plate electrode FP (lead-out portion FPa) is formed inside the outer peripheral trench TR2. The outer peripheral trench TR2 has an extending part TR2a extending in the Y direction, an extending part TR2b extending in the X direction, and a corner part TR2c extending in a direction different from the X and Y directions in plan view and connecting the extending part TR2a and the extending part TR2b. In the Y-direction, the distance L2 between the end part 10 of the closest trench TR1 closest to the extending part TR2a and the extending part TR2b is longer than the distance L3 between the end part 10 of the other trench TR1 and the extending part TR2b.

公开(公告)号：US20180294033A1

公开(公告)日：2018-10-11

申请号：US16009535

申请日：2018-06-15

Applicant: Renesas Electronics Corporation

Inventor： Kenichiro SONODA ,  Eiji TSUKUDA ,  Keiichi MAEKAWA

IPC: G11C16/10 ,  H01L29/792 ,  H01L29/06 ,  H01L27/12 ,  H01L27/11573 ,  H01L27/11568 ,  H01L21/84 ,  G11C16/34 ,  G11C16/04 ,  G11C16/26 ,  G11C16/14 ,  G11C16/08

CPC classification number: G11C16/10 ,  G11C16/0416 ,  G11C16/0466 ,  G11C16/06 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3445 ,  G11C16/3459 ,  H01L21/84 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/792

Abstract: A semiconductor device is provided that is capable of reducing the possibility of change in state of memory elements formed over a semiconductor substrate with an insulating layer interposed therebetween. The semiconductor device includes nonvolatile memory elements and a bias circuit. Each of the nonvolatile memory elements includes a drain region and a source region arranged so as to sandwich a semiconductor region where a channel is formed, a gate electrode, and a charge storage layer arranged between the gate electrode and the semiconductor region. The nonvolatile memory elements are arranged over the semiconductor substrate with the insulating layer interposed therebetween. When electrons are stored in the charge storage layer, the bias circuit reduces the potential difference between the gate electrode and at least one of the drain region and source region in order to decrease holes stored in the channel of a nonvolatile memory element.

公开(公告)号：US20190164847A1

公开(公告)日：2019-05-30

申请号：US16129592

申请日：2018-09-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Keiichi MAEKAWA

IPC: H01L21/8238 ,  H01L29/06 ,  H01L21/3115 ,  H01L25/07

Abstract: To improve reliability of a semiconductor device, in a method of manufacturing the semiconductor device, a ground plane region of an n-type MISFET is formed by ion-implanting a p-type impurity and nitrogen (N) and a ground plane region of a p-type MISFET is formed by ion-implanting an n-type impurity and one of carbon (C) and fluorine (F).

公开(公告)号：US20180040379A1

公开(公告)日：2018-02-08

申请号：US15597294

申请日：2017-05-17

Applicant: Renesas Electronics Corporation

Inventor： Kenichiro SONODA ,  Eiji TSUKUDA ,  Keiichi MAEKAWA

IPC: G11C16/10 ,  H01L27/11573 ,  H01L29/06 ,  G11C16/34 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  H01L27/11568 ,  H01L29/792

CPC classification number: G11C16/10 ,  G11C16/0416 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3445 ,  G11C16/3459 ,  H01L21/84 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/792

Abstract: A semiconductor device is provided that is capable of reducing the possibility of change in state of memory elements formed over a semiconductor substrate with an insulating layer interposed therebetween. The semiconductor device includes nonvolatile memory elements and a bias circuit. Each of the nonvolatile memory elements includes a drain region and a source region arranged so as to sandwich a semiconductor region where a channel is formed, a gate electrode, and a charge storage layer arranged between the gate electrode and the semiconductor region. The nonvolatile memory elements are arranged over the semiconductor substrate with the insulating layer interposed therebetween. When electrons are stored in the charge storage layer, the bias circuit reduces the potential difference between the gate electrode and at least one of the drain region and source region in order to decrease holes stored in the channel of a nonvolatile memory element.

公开(公告)号：US20170263328A1

公开(公告)日：2017-09-14

申请号：US15382646

申请日：2016-12-17

Applicant: Renesas Electronics Corporation

Inventor： Keiichi MAEKAWA ,  Shiro KAMOHARA ,  Yasushi YAMAGATA ,  Yoshiki YAMAMOTO

IPC: G11C17/18 ,  H01L29/36 ,  G11C17/16 ,  H01L21/283 ,  H01L21/768 ,  H01L21/266 ,  H01L27/12 ,  H01L21/84

CPC classification number: G11C17/18 ,  G11C17/16 ,  H01L21/266 ,  H01L21/283 ,  H01L21/76895 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/36

Abstract: To provide a semiconductor device equipped with anti-fuse memory cells, which is capable of improving read-out accuracy of information. There is provided a semiconductor device in which an N channel type memory transistor, a selection core transistor, and a selection bulk transistor are respectively electrically coupled in series. The memory transistor and the selection core transistor are formed in a silicon layer of an SOI substrate, and the selection bulk transistor is formed in a semiconductor substrate. A word line is coupled to a memory gate electrode of the memory transistor, and a bit line is coupled to the selection bulk transistor. A write-in operation is performed while applying a counter voltage opposite in polarity to a voltage applied from the word line to the memory gate electrode to the bit line.