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    Technique for compensating for a difference in deposition behavior in an interlayer dielectric material
    1.
    发明授权
    Technique for compensating for a difference in deposition behavior in an interlayer dielectric material 有权
    补偿层间电介质材料沉积行为差异的技术

    公开(公告)号：US07785956B2

    公开(公告)日：2010-08-31

    申请号：US12168443

    申请日：2008-07-07

    申请人： Ralf Richter ,  Robert Seidel ,  Carsten Peters

    发明人： Ralf Richter ,  Robert Seidel ,  Carsten Peters

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/7843

    摘要： By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop layers of both types of internal stress or may be provided after the deposition of one type of dielectric material and may be used during the subsequent patterning of the other type of dielectric stop material as an efficient etch stop layer.

    摘要翻译： 通过选择性地提供具有适当厚度的缓冲层，在形成先进的半导体器件的层间电介质叠层的过程中，可以减少沉积SACVD二氧化硅期间出现的高度差异。 可以在沉积两种类型的内部应力的接触蚀刻停止层之后选择性地提供缓冲材料，或者可以在沉积一种类型的电介质材料之后提供缓冲材料，并且可以在随后的其它类型的电介质停止材料的图案化期间使用缓冲材料 作为有效的蚀刻停止层。

    TECHNIQUE FOR COMPENSATING FOR A DIFFERENCE IN DEPOSITION BEHAVIOR IN AN INTERLAYER DIELECTRIC MATERIAL
    2.
    发明申请
    TECHNIQUE FOR COMPENSATING FOR A DIFFERENCE IN DEPOSITION BEHAVIOR IN AN INTERLAYER DIELECTRIC MATERIAL 有权
    用于补偿中间层介质材料中沉积行为差异的技术

    公开(公告)号：US20100285668A1

    公开(公告)日：2010-11-11

    申请号：US12841313

    申请日：2010-07-22

    申请人： Ralf Richter ,  Robert Seidel ,  Carsten Peters

    发明人： Ralf Richter ,  Robert Seidel ,  Carsten Peters

    IPC分类号： H01L21/311 ,  H01L21/31

    CPC分类号： H01L21/823807 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/7843

    摘要： By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop layers of both types of internal stress or may be provided after the deposition of one type of dielectric material and may be used during the subsequent patterning of the other type of dielectric stop material as an efficient etch stop layer.

    摘要翻译： 通过选择性地提供具有适当厚度的缓冲层，在形成先进的半导体器件的层间电介质叠层的过程中，可以减少沉积SACVD二氧化硅期间出现的高度差异。 可以在沉积两种类型的内部应力的接触蚀刻停止层之后选择性地提供缓冲材料，或者可以在沉积一种类型的电介质材料之后提供缓冲材料，并且可以在随后的其它类型的电介质停止材料的图案化期间使用缓冲材料 作为有效的蚀刻停止层。

    Technique for compensating for a difference in deposition behavior in an interlayer dielectric material
    3.
    发明授权
    Technique for compensating for a difference in deposition behavior in an interlayer dielectric material 有权
    补偿层间电介质材料沉积行为差异的技术

    公开(公告)号：US07875514B2

    公开(公告)日：2011-01-25

    申请号：US12841313

    申请日：2010-07-22

    申请人： Ralf Richter ,  Robert Seidel ,  Carsten Peters

    发明人： Ralf Richter ,  Robert Seidel ,  Carsten Peters

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/7843

    摘要： By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop layers of both types of internal stress or may be provided after the deposition of one type of dielectric material and may be used during the subsequent patterning of the other type of dielectric stop material as an efficient etch stop layer.

    摘要翻译： 通过选择性地提供具有适当厚度的缓冲层，在形成先进的半导体器件的层间电介质叠层的过程中，可以减少沉积SACVD二氧化硅期间出现的高度差异。 可以在沉积两种类型的内部应力的接触蚀刻停止层之后选择性地提供缓冲材料，或者可以在沉积一种类型的电介质材料之后提供缓冲材料，并且可以在随后的其它类型的电介质停止材料的图案化期间使用缓冲材料 作为有效的蚀刻停止层。

    TECHNIQUE FOR COMPENSATING FOR A DIFFERENCE IN DEPOSITION BEHAVIOR IN AN INTERLAYER DIELECTRIC MATERIAL
    4.
    发明申请
    TECHNIQUE FOR COMPENSATING FOR A DIFFERENCE IN DEPOSITION BEHAVIOR IN AN INTERLAYER DIELECTRIC MATERIAL 有权
    用于补偿中间层介质材料中沉积行为差异的技术

    公开(公告)号：US20090087999A1

    公开(公告)日：2009-04-02

    申请号：US12168443

    申请日：2008-07-07

    申请人： Ralf Richter ,  Robert Seidel ,  Carsten Peters

    发明人： Ralf Richter ,  Robert Seidel ,  Carsten Peters

    IPC分类号： H01L21/31

    CPC分类号： H01L21/823807 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/7843

    摘要： By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop layers of both types of internal stress or may be provided after the deposition of one type of dielectric material and may be used during the subsequent patterning of the other type of dielectric stop material as an efficient etch stop layer.

    摘要翻译： 通过选择性地提供具有适当厚度的缓冲层，在形成先进的半导体器件的层间电介质叠层的过程中，可以减少沉积SACVD二氧化硅期间出现的高度差异。 可以在沉积两种类型的内部应力的接触蚀刻停止层之后选择性地提供缓冲材料，或者可以在沉积一种类型的电介质材料之后提供缓冲材料，并且可以在随后的其它类型的电介质停止材料的图案化期间使用缓冲材料 作为有效的蚀刻停止层。

    Semiconductor device and method for patterning vertical contacts and metal lines in a common etch process
    6.
    发明授权
    Semiconductor device and method for patterning vertical contacts and metal lines in a common etch process 有权
    在普通蚀刻工艺中用于图案化垂直接触和金属线的半导体器件和方法

    公开(公告)号：US08741770B2

    公开(公告)日：2014-06-03

    申请号：US13468083

    申请日：2012-05-10

    申请人： Ralf Richter ,  Robert Seidel ,  Juergen Boemmels ,  Thomas Foltyn

    发明人： Ralf Richter ,  Robert Seidel ,  Juergen Boemmels ,  Thomas Foltyn

    IPC分类号： H01L23/48 ,  H01L21/4763

    CPC分类号： H01L21/7681 ,  H01L21/76811 ,  H01L21/76816

    摘要： Interlayer connections, i.e., vertical connections, may be formed on the basis of a hard mask material, which may be positioned below, within or above an interlayer dielectric material, wherein one lateral dimension is defined by a trench mask, thereby obtaining a desired interlayer connection in a common patterning process. Furthermore, the thickness of at least certain portions of the metal lines may be adjusted with a high degree of flexibility, thereby providing the possibility of significantly reducing the overall resistivity of metal lines in metal levels, in which device performance may significantly depend on resistivity rather than parasitic capacitance.

    摘要翻译： 中间层连接（即垂直连接）可以基于硬掩模材料形成，硬掩模材料可以位于层间电介质材料的内部或之上，其中一个横向尺寸由沟槽掩模限定，从而获得所需的中间层 连接在共同的图案化过程中。 此外，金属线的至少某些部分的厚度可以以高度的柔性来调节，从而提供了显着降低金属线中金属线的整体电阻率的可能性，其中器件性能可能显着地取决于电阻率 比寄生电容。

    Technique for reducing topography-related irregularities during the patterning of a dielectric material in a contact level of closely spaced transistors
    7.
    发明授权
    Technique for reducing topography-related irregularities during the patterning of a dielectric material in a contact level of closely spaced transistors 失效
    在紧密间隔的晶体管的接触电平中的介电材料的图案化期间减小与形貌相关的不规则性的技术

    公开(公告)号：US08338314B2

    公开(公告)日：2012-12-25

    申请号：US12372006

    申请日：2009-02-17

    申请人： Ralf Richter ,  Heike Salz ,  Robert Seidel

    发明人： Ralf Richter ,  Heike Salz ,  Robert Seidel

    IPC分类号： H01L21/31

    CPC分类号： H01L21/02107 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/51 ,  H01L29/7843 ,  H01L29/7848 ,  Y02P80/30

    摘要： In a dual stress liner approach, the surface conditions after the patterning of a first stress-inducing layer may be enhanced by appropriately designing an etch sequence for substantially completely removing an etch stop material, which may be used for the patterning of the second stress-inducing dielectric material, while, in other cases, the etch stop material may be selectively formed after the patterning of the first stress-inducing dielectric material. Hence, the dual stress liner approach may be efficiently applied to semiconductor devices of the 45 nm technology and beyond.

    摘要翻译： 在双重应力衬垫方法中，可以通过适当地设计用于基本上完全去除蚀刻停止材料的蚀刻顺序来增强第一应力诱导层的图案化之后的表面状态，所述蚀刻顺序可用于图案化第二应力 - 诱导介电材料，而在其它情况下，可以在第一应力诱导电介质材料的图案化之后选择性地形成蚀刻停止材料。 因此，双重应力衬垫方法可以有效地应用于45nm技术及其以外的半导体器件。