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    Successive approximation register analog-to-digital converter chopping
    4.
    发明授权
    Successive approximation register analog-to-digital converter chopping 有权

    公开(公告)号：US10461762B1

    公开(公告)日：2019-10-29

    申请号：US16051686

    申请日：2018-08-01

    Applicant: QUALCOMM Incorporated

    Inventor： Mohammad Meysam Zargham ,  Yan Wang ,  Li Lu ,  Dinesh Jagannath Alladi

    IPC: H03M1/06 ,  H03M1/00

    Abstract: Methods and apparatuses for chopping a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC generally includes a comparator comprising a first input and a second input; a switch connected between the first and second inputs of the comparator; a first capacitive array having a first terminal selectively coupled to the first input of the comparator; a second capacitive array having a first terminal selectively coupled to the second input of the comparator; and a reference buffer selectively coupled to second terminals of the first and second capacitive arrays and configured to apply inverse digital codes to the first and second capacitive arrays, wherein the switch is configured to short the first and second inputs of the comparator while the inverse digital codes are being applied to the first and second capacitive arrays such that charges of the first and second capacitive arrays are redistributed via the reference buffer.

    Continuous-time analog-to-digital converter
    5.
    发明授权
    Continuous-time analog-to-digital converter 有权

    公开(公告)号：US10277241B1

    公开(公告)日：2019-04-30

    申请号：US15961631

    申请日：2018-04-24

    Applicant: QUALCOMM Incorporated

    Inventor： Omid Rajaee ,  Elias Dagher ,  Yan Wang ,  Dinesh Jagannath Alladi

    IPC: H03M1/18 ,  H03M1/66 ,  H03M3/00

    Abstract: A continuous-time analog-to-digital converter (ADC) includes a plurality of integrators selectively coupled in series. The ADC may further include a quantizer with excess loop delay (ELD) compensation. The quantizer may be coupled in series to a least one integrator. The ELD compensation may be programmable based on a transfer function of the ADC. The ADC may further include parallel digital-to-analog converters (DACs). Each DAC may have an input coupled to an output of the quantizer, and an output coupled to an input of a corresponding integrator. The ADC may further include a bypass path coupled to an input or output of one of the integrators. The bypass path may be configured to selectively bypass one or more of the integrators to change the transfer function of the ADC.

    Area-efficient non-overlapping signal generator
    7.
    发明授权
    Area-efficient non-overlapping signal generator 有权

    公开(公告)号：US10886904B1

    公开(公告)日：2021-01-05

    申请号：US16752412

    申请日：2020-01-24

    Applicant: QUALCOMM Incorporated

    Inventor： Qubo Zhou ,  Yan Wang

    IPC: H03K5/134 ,  H03K19/003 ,  H03K19/0185

    Abstract: Certain aspects of the present disclosure generally relate to a power stage. The power stage generally includes a first transistor, a second transistor having a drain coupled to a drain of the first transistor, a first gate drive circuit coupled between an input node of the power stage and a gate of the first transistor, and a second gate drive circuit having a first signal path coupled between the input node and a gate of the second transistor. In certain aspects, the second gate drive circuit comprises a plurality of buffers in the first signal path, and a plurality of electronic devices coupled to the plurality of buffers and configured to apply a delay associated with driving the gate of the second transistor to track a delay associated with driving the gate of the first transistor via the first gate drive circuit.

    Power efficient noise-coupled delta-sigma modulator
    8.
    发明授权
    Power efficient noise-coupled delta-sigma modulator 有权
    功率有效的噪声耦合Δ-Σ调制器

    公开(公告)号：US09184765B1

    公开(公告)日：2015-11-10

    申请号：US14485641

    申请日：2014-09-12

    Applicant: QUALCOMM Incorporated

    Inventor： Yan Wang ,  Qubo Zhou

    IPC: H03M3/00 ,  H03M1/12 ,  H04N19/126 ,  H03M1/00

    CPC classification number: H03M3/45 ,  H03M3/424

    Abstract: A method and apparatus for a feed-forward delta-sigma modulator are provided. The apparatus includes a first adder configured to receive a feedback signal and an input signal and a first integrator configured to receive an output from the first adder. The apparatus also includes a noise-coupled summer/integrator (NCSI). The NCSI includes a second adder configured to receive a differentiation path from the first integrator, an output from the first integrator, and a delayed feedback path from the output of a second integrator. The NCSI also includes the second integrator configured to receive an output from the second adder. The apparatus also includes a quantizer configured to receive the output of the second integrator, feed back the output to the first adder and the NCSI and produce the output from the feed-forward delta-sigma modulator.

    Abstract translation: 提供了一种用于前馈delta-sigma调制器的方法和装置。 该装置包括：第一加法器，被配置为接收反馈信号和输入信号;以及第一积分器，被配置为接收来自第一加法器的输出。 该装置还包括噪声耦合的加法器/积分器（NCSI）。 NCSI包括第二加法器，其被配置为从第一积分器接收微分路径，来自第一积分器的输出和来自第二积分器的输出的延迟反馈路径。 NCSI还包括被配置为从第二加法器接收输出的第二积分器。 该装置还包括被配置为接收第二积分器的输出的量化器，将输出反馈到第一加法器和NCSI并产生来自前馈delta-sigma调制器的输出。

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