知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

18 records (took 0.015 seconds)

    Frequency divider with duty cycle adjustment within feedback loop
    2.
    发明授权
    Frequency divider with duty cycle adjustment within feedback loop 有权
    分频器在反馈环路内进行占空比调整

    公开(公告)号：US09379722B2

    公开(公告)日：2016-06-28

    申请号：US13926631

    申请日：2013-06-25

    Applicant: QUALCOMM Incorporated

    Inventor： Wu-Hsin Chen ,  Sriramgopal Sridhara ,  Li Liu

    IPC: H03K21/00 ,  H03K23/00 ,  H03K25/00 ,  H03L7/18 ,  H03K3/017 ,  H03K5/156 ,  H03K21/08

    CPC classification number: H03L7/18 ,  H03K3/017 ,  H03K5/1565 ,  H03K21/08

    Abstract: A frequency divider with duty cycle adjustment within a feedback loop is disclosed. In an exemplary design, an apparatus includes at least one divider circuit and at least one duty cycle adjustment circuit coupled in a feedback loop. The divider circuit(s) receive a clock signal at a first frequency and provide at least one divided signal at a second frequency, which is a fraction of the first frequency. The duty cycle adjustment circuit(s) adjust the duty cycle of the at least one divided signal and provide at least one duty cycle adjusted signal to the divider circuit(s). The divider circuit(s) may include first and second latches, and the duty cycle adjustment circuit(s) may include first and second duty cycle adjustment circuits. The first and second latches and the first and second duty cycle adjustment circuits may be coupled in a feedback loop and may perform divide-by-2.

    Abstract translation: 公开了一种在反馈环路内进行占空比调节的分频器。 在示例性设计中，装置包括耦合在反馈回路中的至少一个除法器电路和至少一个占空比调整电路。 分频器电路以第一频率接收时钟信号，并以第二频率提供至少一个分频信号，该第二频率是第一频率的一部分。 占空比调整电路调整至少一个分频信号的占空比，并向分频器电路提供至少一个占空比调整信号。 分频器电路可以包括第一和第二锁存器，并且占空比调整电路可以包括第一和第二占空比调整电路。 第一和第二锁存器以及第一和第二占空比调整电路可以耦合在反馈回路中并且可以执行除以2。

    FREQUENCY DIVIDER WITH DUTY CYCLE ADJUSTMENT WITHIN FEEDBACK LOOP
    5.
    发明申请
    FREQUENCY DIVIDER WITH DUTY CYCLE ADJUSTMENT WITHIN FEEDBACK LOOP 有权
    频率分频器在反馈环路中进行占空比调整

    公开(公告)号：US20140375363A1

    公开(公告)日：2014-12-25

    申请号：US13926631

    申请日：2013-06-25

    Applicant: QUALCOMM Incorporated

    Inventor： Wu-Hsin Chen ,  Sriramgopal Sridhara ,  Li Liu

    IPC: H03L7/18

    CPC classification number: H03L7/18 ,  H03K3/017 ,  H03K5/1565 ,  H03K21/08

    Abstract: A frequency divider with duty cycle adjustment within a feedback loop is disclosed. In an exemplary design, an apparatus includes at least one divider circuit and at least one duty cycle adjustment circuit coupled in a feedback loop. The divider circuit(s) receive a clock signal at a first frequency and provide at least one divided signal at a second frequency, which is a fraction of the first frequency. The duty cycle adjustment circuit(s) adjust the duty cycle of the at least one divided signal and provide at least one duty cycle adjusted signal to the divider circuit(s). The divider circuit(s) may include first and second latches, and the duty cycle adjustment circuit(s) may include first and second duty cycle adjustment circuits. The first and second latches and the first and second duty cycle adjustment circuits may be coupled in a feedback loop and may perform divide-by-2.

    Abstract translation: 公开了一种在反馈环路内进行占空比调节的分频器。 在示例性设计中，装置包括耦合在反馈回路中的至少一个除法器电路和至少一个占空比调整电路。 分频器电路以第一频率接收时钟信号，并以第二频率提供至少一个分频信号，该第二频率是第一频率的一部分。 占空比调整电路调整至少一个分频信号的占空比，并向分频器电路提供至少一个占空比调整信号。 分频器电路可以包括第一和第二锁存器，并且占空比调整电路可以包括第一和第二占空比调整电路。 第一和第二锁存器以及第一和第二占空比调整电路可以耦合在反馈回路中并且可以执行除以2。

    PSEUDO-CML LATCH AND DIVIDER HAVING REDUCED CHARGE SHARING BETWEEN OUTPUT NODES
    8.
    发明申请
    PSEUDO-CML LATCH AND DIVIDER HAVING REDUCED CHARGE SHARING BETWEEN OUTPUT NODES 有权
    PSEUDO-CML LATCH和DIVIDER在输出节点之间具有减少的充电共享

    公开(公告)号：US20140375367A1

    公开(公告)日：2014-12-25

    申请号：US13926680

    申请日：2013-06-25

    Applicant: QUALCOMM Incorporated

    Inventor： Wu-Hsin Chen ,  Li Liu ,  Jianyun Hu

    IPC: H03K3/017 ,  H01L21/8238

    CPC classification number: H03K3/017 ,  H01L21/823871 ,  H03K3/356121 ,  H03K3/356139

    Abstract: In one example, a high-speed divider includes two identical pseudo-CML latches and four output inverters. Each latch includes a pair of cross-coupled signal holding transistors. A first P-channel pull-up circuit pulls up on a second output node QB of the latch. A second P-channel pull-up circuit pulls up on a first output node Q of the latch. A pull-down circuit involves four N-channel transistors. This pull-down circuit: 1) couples the QB node to ground when a clock signal CK is high and a data signal D is high, 2) couples the Q node to ground when CK is high and D is low, 3) prevents a transfer of charge between the QB and Q nodes through the pull-down circuit when D transitions during a time period when CK is low, and 4) decouples the QB and Q nodes from the pull-down circuit when CK is low.

    Abstract translation: 在一个示例中，高速分频器包括两个相同的伪CML锁存器和四个输出反相器。 每个锁存器包括一对交叉耦合的信号保持晶体管。 第一P沟道上拉电路在锁存器的第二输出节点QB上拉起。 第二P沟道上拉电路在锁存器的第一输出节点Q上拉起。 下拉电路包括四个N沟道晶体管。 该下拉电路：1）当时钟信号CK为高电平且数据信号D为高电平时，将QB节点耦合到地，2）当CK为高电平且D为低电平时将Q节点接地，3）防止 当CK为低电平时，D转换时，通过下拉电路在QB和Q节点之间传输电荷;以及4）当CK为低电平时，将QB和Q节点与下拉电路解耦。

    Split chaining for large phase array systems
    10.
    发明授权
    Split chaining for large phase array systems 有权

    公开(公告)号：US11942971B2

    公开(公告)日：2024-03-26

    申请号：US17686794

    申请日：2022-03-04

    Applicant: QUALCOMM Incorporated

    Inventor： Chuan Wang ,  Li Liu ,  Wu-Hsin Chen ,  Vinod Panikkath ,  Yunfei Feng ,  Muhammad Hassan

    IPC: H04B1/00 ,  H04B1/04 ,  H04B1/10

    CPC classification number: H04B1/0057 ,  H04B1/0035 ,  H04B1/0483 ,  H04B2001/0408

    Abstract: Aspects described herein include devices and methods with chain routing of signals for massive antenna arrays. In some aspects, an apparatus is provided that includes a first millimeter wave (mmW) transceiver having a first port, a second port, one or more antenna elements, a plurality of chain mmW transceiver ports, and switching circuitry. The switching circuitry is controllable by control data to route portions of a merged clock and data signal and a merged control and data signal between a first route between the one or more antenna elements and the first port and a second route between the one or more antenna elements and the second port and a third route between the first port and the plurality of chain mmW transceiver ports and a fourth route between the second port and the plurality of chain mmW transceiver ports.

Patent Agency Ranking