公开(公告)号：US20160358910A1

公开(公告)日：2016-12-08

申请号：US15240009

申请日：2016-08-18

Applicant: QUALCOMM Incorporated

Inventor： Michael Andrew Stuber ,  Stuart Molin

IPC: H01L27/082 ,  H01L29/739 ,  H01L29/78 ,  H01L29/10 ,  H01L29/744

CPC classification number: H01L27/0823 ,  H01L21/6835 ,  H01L21/823487 ,  H01L23/481 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L27/088 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66363 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/73 ,  H01L29/7317 ,  H01L29/732 ,  H01L29/7394 ,  H01L29/7395 ,  H01L29/744 ,  H01L29/7802 ,  H01L29/781 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/056 ,  H01L2224/05638 ,  H01L2224/1148 ,  H01L2224/1302 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/48 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/01014 ,  H01L2924/00

Abstract: A vertical semiconductor device is formed in a semiconductor layer having a first surface, a second surface and background doping. A first doped region, doped to a conductivity type opposite that of the background, is formed at the second surface of the semiconductor layer. A second doped region of the same conductivity type as the background is formed at the second surface of the semiconductor layer, inside the first doped region. A portion of the semiconductor layer is removed at the first surface, exposing a new third surface. A third doped region is formed inside the semiconductor layer at the third surface. Electrical contact is made at least to the second doped region (via the second surface) and the third doped region (via the new third surface). In this way, vertical DMOS, IGBT, bipolar transistors, thyristors, and other types of devices can be fabricated in thinned semiconductor, or SOI layers.

Abstract translation: 在具有第一表面，第二表面和背景掺杂的半导体层中形成垂直半导体器件。 在半导体层的第二表面形成掺杂到与背景相反的导电类型的第一掺杂区域。 在第一掺杂区域的内部，在半导体层的第二表面形成与背景相同导电类型的第二掺杂区域。 半导体层的一部分在第一表面被去除，暴露出新的第三表面。 第三掺杂区域形成在第三表面的半导体层的内部。 至少对第二掺杂区域（经由第二表面）和第三掺杂区域（经由新的第三表面）进行电接触。 以这种方式，可以在减薄的半导体或SOI层中制造垂直DMOS，IGBT，双极晶体管，晶闸管和其他类型的器件。