公开(公告)号：US11797045B2

公开(公告)日：2023-10-24

申请号：US17666420

申请日：2022-02-07

Applicant: QUALCOMM Incorporated

Inventor： Jonathan Masters ,  Pradeep Kanapathipillai ,  Manu Gulati ,  Nitin Makhija

IPC: G06F1/12 ,  G06F1/08 ,  G06F11/34 ,  G06F11/30 ,  G06F1/3206

CPC classification number: G06F1/12 ,  G06F1/08 ,  G06F1/3206 ,  G06F11/3062 ,  G06F11/3409

Abstract: An electronic system has a plurality of processing clusters including a first processing cluster. The first processing cluster further includes a plurality of processors and a power management processor. The power management processor obtains performance information about the plurality of processors, executes power instructions to transition a first processor of the plurality of processors from a first performance state to a second performance state different from the first performance state, and executes one or more debug instructions to perform debugging of a respective processor of the plurality of processors. The power instructions are executed in accordance with the obtained performance information and independently of respective performance states of other processors in the plurality of processors of the first processing cluster. In some implementations, the power management processor receives, from a system controller external to the plurality of processing clusters, a first power allocation for the first processing cluster.

公开(公告)号：US20250093942A1

公开(公告)日：2025-03-20

申请号：US18469890

申请日：2023-09-19

Applicant: QUALCOMM Incorporated

Inventor： Mahadevamurty Nemani ,  Adarsh Baraka Ravi ,  Nitin Makhija ,  Pradeep Kanapathipillai

IPC: G06F1/3296 ,  G06F1/3206

Abstract: Power sources provide power in a range with a maximum supply voltage provided under zero-load current conditions. Power circuits in an IC receive and aggregate indications of load current from processor circuits in processor circuit clusters and, reduce power consumption in the IC during zero or low load current conditions by generating a voltage control signal to reduce the supply voltage. Reducing the no-load voltage also reduces stress on gate oxides of transistors in the IC to increase oxide longevity. Based on the aggregated load current indications, which is periodically updated, the no-load supply voltage may be incrementally reduced down to a voltage threshold over the course of multiple periods. In some examples, the power circuits receive throttle signals when the processor circuits are throttled due to a voltage droop, and such signals may cause the power circuits to generate a control signal to increase the no-load voltage.

公开(公告)号：US20240427682A1

公开(公告)日：2024-12-26

申请号：US18339520

申请日：2023-06-22

Applicant: QUALCOMM Incorporated

Inventor： Sagar Koorapati ,  Pradeep Kanapathipillai ,  Alon Naveh

IPC: G06F11/30 ,  G06F1/3206

Abstract: Converting telemetry values into common data formats in a processor-based system in an integrated circuit (IC) chip is disclosed herein. In one aspect, an IC chip comprises a processor-based system that that is configured to receive an input telemetry value from an input source circuit. The processor-based system converts the input telemetry value into a common format telemetry value, wherein a first unit value represented by a least significant bit of the common format telemetry value is greater than one (1) and is based on a quotient of a power of two (2) and a corresponding power of 10. The processor-based system then processes common format telemetry value.

公开(公告)号：US11914524B2

公开(公告)日：2024-02-27

申请号：US17684231

申请日：2022-03-01

Applicant: QUALCOMM Incorporated

Inventor： Adrian Montero ,  Huzefa Sanjeliwala ,  Paul Kitchin ,  Prarthna Santhanakrishnan ,  Conrado Blasco ,  Pradeep Kanapathipillai

IPC: G06F12/1036 ,  G06F9/30 ,  G06F9/455

CPC classification number: G06F12/1036 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/45558 ,  G06F2009/45562

Abstract: An electronic device includes one or more processors for executing one or more virtual machines. In response to a request for initiating a synchronization event, a processor identifies a subset of speculative memory access requests in one or more memory access request queues. Automatically and in accordance with the identifying, the processor purges translations associated with the subset of speculative memory access requests. Subsequent to the purging, the processor initiates the synchronization event. In some implementations, memory access completion is forced in response to a context synchronization event that corresponds to a termination of a first application, a termination of a first virtual machine, or a system call for updating a system register. Alternatively, in some implementations, memory access completion is forced in an operating system level or an application level in response to a data synchronization event that is initiated on a hypervisor layer or a firmware layer.