公开(公告)号：US11797045B2

公开(公告)日：2023-10-24

申请号：US17666420

申请日：2022-02-07

Applicant: QUALCOMM Incorporated

Inventor： Jonathan Masters ,  Pradeep Kanapathipillai ,  Manu Gulati ,  Nitin Makhija

IPC: G06F1/12 ,  G06F1/08 ,  G06F11/34 ,  G06F11/30 ,  G06F1/3206

CPC classification number: G06F1/12 ,  G06F1/08 ,  G06F1/3206 ,  G06F11/3062 ,  G06F11/3409

Abstract: An electronic system has a plurality of processing clusters including a first processing cluster. The first processing cluster further includes a plurality of processors and a power management processor. The power management processor obtains performance information about the plurality of processors, executes power instructions to transition a first processor of the plurality of processors from a first performance state to a second performance state different from the first performance state, and executes one or more debug instructions to perform debugging of a respective processor of the plurality of processors. The power instructions are executed in accordance with the obtained performance information and independently of respective performance states of other processors in the plurality of processors of the first processing cluster. In some implementations, the power management processor receives, from a system controller external to the plurality of processing clusters, a first power allocation for the first processing cluster.