公开(公告)号：US20240273034A1

公开(公告)日：2024-08-15

申请号：US18168871

申请日：2023-02-14

Applicant: QUALCOMM Incorporated

Inventor： Adrian Montero ,  Conrado Blasco ,  Paul Kitchin ,  Huzefa Sanjeliwala

IPC: G06F12/1027 ,  G06F9/455

CPC classification number: G06F12/1027 ,  G06F9/45558 ,  G06F2009/45583

Abstract: Compressing translation lookaside buffer (TLB) tags using a TLB metadata buffer in processor-based devices is disclosed herein. In some aspects, a processor-based device provides a memory management unit (MMU) that includes a TLB and a TLB metadata buffer comprising a plurality of TLB metadata buffer entries storing corresponding TLB metadata. The MMU is configured to select a TLB metadata buffer entry for use in accessing the TLB of the processor-based device. After selecting the TLB metadata buffer entry, the MMU stores a pointer to the TLB metadata buffer entry as an active TLB metadata pointer. When the MMU subsequently receives a memory access request comprising a virtual address (VA), the MMU generates a TLB entry in the TLB for the VA, and stores the active TLB metadata pointer as part of the TLB tag of the TLB entry in lieu of the TLB metadata of the TLB metadata buffer entry.

公开(公告)号：US20240385841A1

公开(公告)日：2024-11-21

申请号：US18594899

申请日：2024-03-04

Applicant: QUALCOMM Incorporated

Inventor： Conrado Blasco ,  Ajay Kumar Rathee ,  Huzefa Sanjeliwala

IPC: G06F9/38

Abstract: Fetching beyond predicted-taken branch instructions in fetch bundles of processor-based devices is disclosed. In exemplary aspects, a processor-based device comprises an instruction processing circuit configured to process an instruction stream in an instruction pipeline. The instruction processing circuit comprises an instruction fetch circuit configured to generate a fetch bundle comprising a plurality of fetched instructions from the instruction stream, wherein a last fetched instruction of the plurality of fetched instructions is a predicted-taken branch instruction. The instruction processing circuit is further configured to identify the plurality of fetched instructions as a loop iteration. The instruction processing circuit is also configured to determine that at least one loop iteration copy fits within the fetch bundle. The instruction processing circuit is additionally configured to, responsive to determining that the at least one loop iteration copy fits within the fetch bundle, store the at least one loop iteration copy within the fetch bundle.

公开(公告)号：US20240086526A1

公开(公告)日：2024-03-14

申请号：US18067825

申请日：2022-12-19

Applicant: QUALCOMM Incorporated

Inventor： Jamie David Iles ,  Conrado Blasco

IPC: G06F21/55 ,  G06F21/54 ,  G06F21/56

CPC classification number: G06F21/554 ,  G06F21/54 ,  G06F21/566

Abstract: Mitigating Pointer Authentication Code (PAC) attacks in processor-based devices is disclosed herein. In this regard, in some exemplary aspects, a processor of a processor-based device is configured to determine that a pointer authentication instruction to authenticate a pointer is being executed speculatively. The processor is further configured to, responsive to determining that the pointer authentication instruction is being executed speculatively, determine, based on a signature of the pointer, that the pointer is not valid. The processor is also configured to, responsive to determining that the pointer is not valid, perform a mitigation action.

公开(公告)号：US11914524B2

公开(公告)日：2024-02-27

申请号：US17684231

申请日：2022-03-01

Applicant: QUALCOMM Incorporated

Inventor： Adrian Montero ,  Huzefa Sanjeliwala ,  Paul Kitchin ,  Prarthna Santhanakrishnan ,  Conrado Blasco ,  Pradeep Kanapathipillai

IPC: G06F12/1036 ,  G06F9/30 ,  G06F9/455

CPC classification number: G06F12/1036 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/45558 ,  G06F2009/45562

Abstract: An electronic device includes one or more processors for executing one or more virtual machines. In response to a request for initiating a synchronization event, a processor identifies a subset of speculative memory access requests in one or more memory access request queues. Automatically and in accordance with the identifying, the processor purges translations associated with the subset of speculative memory access requests. Subsequent to the purging, the processor initiates the synchronization event. In some implementations, memory access completion is forced in response to a context synchronization event that corresponds to a termination of a first application, a termination of a first virtual machine, or a system call for updating a system register. Alternatively, in some implementations, memory access completion is forced in an operating system level or an application level in response to a data synchronization event that is initiated on a hypervisor layer or a firmware layer.

公开(公告)号：US20240427599A1

公开(公告)日：2024-12-26

申请号：US18339529

申请日：2023-06-22

Applicant: QUALCOMM Incorporated

Inventor： Akilesh Krishnamurthy ,  Conrado Blasco ,  Paul Kitchin ,  Aniket Bhivasen Bhor

IPC: G06F9/30 ,  G06F9/38

Abstract: Providing physical register (PR) swap memory renaming in processor-based devices is disclosed herein. In some exemplary aspects, a processor provides an instruction processing circuit comprising a scheduling stage circuit and an execution stage circuit. The scheduling stage circuit comprises a reservation station circuit, while the execution stage circuit comprises a PR swap table storing a plurality of PR swap table entries. The scheduling stage circuit issues a first instruction that is associated with a store dependency ID. The execution stage circuit, in response to the issuing of the first instruction, identifies a PR swap table entry among the plurality of PR swap table entries corresponding to the store dependency ID, retrieves a load dependency ID of the PR swap table entry, and broadcasts the load dependency ID to the reservation station circuit to wake a second instruction that is associated with the load dependency ID.

公开(公告)号：US12130751B2

公开(公告)日：2024-10-29

申请号：US18168871

申请日：2023-02-14

Applicant: QUALCOMM Incorporated

Inventor： Adrian Montero ,  Conrado Blasco ,  Paul Kitchin ,  Huzefa Sanjeliwala

IPC: G06F12/1027 ,  G06F9/455

CPC classification number: G06F12/1027 ,  G06F9/45558 ,  G06F2009/45583

Abstract: Compressing translation lookaside buffer (TLB) tags using a TLB metadata buffer in processor-based devices is disclosed herein. In some aspects, a processor-based device provides a memory management unit (MMU) that includes a TLB and a TLB metadata buffer comprising a plurality of TLB metadata buffer entries storing corresponding TLB metadata. The MMU is configured to select a TLB metadata buffer entry for use in accessing the TLB of the processor-based device. After selecting the TLB metadata buffer entry, the MMU stores a pointer to the TLB metadata buffer entry as an active TLB metadata pointer. When the MMU subsequently receives a memory access request comprising a virtual address (VA), the MMU generates a TLB entry in the TLB for the VA, and stores the active TLB metadata pointer as part of the TLB tag of the TLB entry in lieu of the TLB metadata of the TLB metadata buffer entry.

公开(公告)号：US20240273035A1

公开(公告)日：2024-08-15

申请号：US18623242

申请日：2024-04-01

Applicant: QUALCOMM Incorporated

Inventor： Adrian Montero ,  Sushmitha Ayyanar ,  Conrado Blasco

IPC: G06F12/1027

CPC classification number: G06F12/1027 ,  G06F2212/1016

Abstract: Exploiting virtual address (VA) spatial locality using translation lookaside buffer (TLB) entry compression in processor-based devices is disclosed herein. In some aspects, a processor-based device comprises a TLB, comprising multiple TLB entries each comprising a tag and a plurality of data portions, and further comprises a memory management unit (MMU). The MMU is configured to receive a memory access request comprising a VA, and determine that a TLB access to the TLB for a page VA of the VA results in a miss. In response, the MMU generates a TLB entry, wherein the tag of the TLB entry comprises the page VA, the plurality of data portions comprises a corresponding plurality of page PAs, a first data portion thereof comprising a page PA corresponding to the page VA, and one or more second data portions thereof comprising corresponding PAs of next sequential page VAs following the page VA.

公开(公告)号：US20240273033A1

公开(公告)日：2024-08-15

申请号：US18168857

申请日：2023-02-14

Applicant: QUALCOMM Incorporated

Inventor： Adrian Montero ,  Sushmitha Ayyanar ,  Conrado Blasco

IPC: G06F12/1027

CPC classification number: G06F12/1027 ,  G06F2212/1016

Abstract: Exploiting virtual address (VA) spatial locality using translation lookaside buffer (TLB) entry compression in processor-based devices is disclosed herein. In some aspects, a processor-based device comprises a TLB, comprising multiple TLB entries each comprising a tag and a plurality of data portions, and further comprises a memory management unit (MMU). The MMU is configured to receive a memory access request comprising a VA, and determine that a TLB access to the TLB for a page VA of the VA results in a miss. In response, the MMU generates a TLB entry, wherein the tag of the TLB entry comprises the page VA, the plurality of data portions comprises a corresponding plurality of page PAs, a first data portion thereof comprising a page PA corresponding to the page VA, and one or more second data portions thereof comprising corresponding PAs of next sequential page VAs following the page VA.

公开(公告)号：US20240264949A1

公开(公告)日：2024-08-08

申请号：US18626488

申请日：2024-04-04

Applicant: QUALCOMM Incorporated

Inventor： Ajay Kumar Rathee ,  Conrado Blasco

IPC: G06F12/1027 ,  G06F12/1009

CPC classification number: G06F12/1027 ,  G06F12/1009 ,  G06F2212/1021

Abstract: Using retired pages history for instruction translation lookaside buffer (TLB) prefetching in processor-based devices is disclosed herein. In some exemplary aspects, a processor-based device is provided. The processor-based device comprises a history-based instruction TLB prefetcher (HTP) circuit configured to determine that a first instruction of a first page has been retired. The HTP circuit is further configured to determine a first page virtual address (VA) of the first page. The HTP circuit is also configured to determine that the first page VA differs from a value of a last retired page VA indicator of the HTP circuit. The HTP circuit is additionally configured to, responsive to determining that the first page VA differs from the value of the last retired page VA indicator of the HTP circuit, store the first page VA as the value of the last retired page VA indicator.

公开(公告)号：US20240241951A1

公开(公告)日：2024-07-18

申请号：US18623516

申请日：2024-04-01

Applicant: QUALCOMM Incorporated

Inventor： Jamie David Iles ,  Conrado Blasco

IPC: G06F21/55 ,  G06F21/54 ,  G06F21/56

CPC classification number: G06F21/554 ,  G06F21/54 ,  G06F21/566

Abstract: Mitigating Pointer Authentication Code (PAC) attacks in processor-based devices is disclosed herein. In this regard, in some exemplary aspects, a processor of a processor-based device is configured to determine that a pointer authentication instruction to authenticate a pointer is being executed speculatively. The processor is further configured to, responsive to determining that the pointer authentication instruction is being executed speculatively, determine, based on a signature of the pointer, that the pointer is not valid. The processor is also configured to, responsive to determining that the pointer is not valid, perform a mitigation action.