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19 条记录 (耗时 0.016 秒)

    Variable delay
    1.
    发明授权
    Variable delay 有权

    公开(公告)号：US10469091B2

    公开(公告)日：2019-11-05

    申请号：US15711924

    申请日：2017-09-21

    申请人： Qualcomm Incorporated

    发明人： Masoud Roham

    IPC分类号： H03L7/06 ,  H03L7/081 ,  H03L7/18 ,  H03L7/08 ,  H03K5/131 ,  H03L7/089 ,  H03L7/189 ,  H03D3/24 ,  H03K5/135 ,  H03L7/07 ,  H03L7/099

    摘要： This disclosure describes controlling a variable delay system with a control signal generated in a phase-locked loop (PLL). Furthermore, aspects describe generating a compensation current based on a number of edges of pulses propagating through a variable delay line including multiple delay elements. The number of edges propagating through the variable delay is determined by computing a difference between a number of edges entering the variable delay line and a number of edges exiting the variable delay line. The compensation current is derived from a mirrored version of the current of the control signal of the PLL. Thus, the techniques and systems in this disclosure provide accurate and repeatable control of a variable delay line over variations in temperature and process using low-power circuits. Furthermore, the input signal to the variable delay line may be asynchronous with respect to a system clock or a reference signal of the PLL.

    Closed loop linearized VCO-based ADC
    3.
    发明授权
    Closed loop linearized VCO-based ADC 有权
    闭环线性化基于VCO的ADC

    公开(公告)号：US09379731B1

    公开(公告)日：2016-06-28

    申请号：US14863200

    申请日：2015-09-23

    申请人： QUALCOMM Incorporated

    发明人： Masoud Roham ,  Mohammad Meysam Zargham ,  Li Lu

    IPC分类号： H03M1/12 ,  H03M1/60

    CPC分类号： H03M1/60 ,  G01K7/16 ,  H03K21/38 ,  H03M1/0612 ,  H03M1/0678 ,  H03M1/089

    摘要： A device and method for analog to digital conversion is disclosed. The device can have a first amplifier operable to receive an input voltage and output a first control signal. The device can also have a first voltage-controlled oscillator (VCO) operably coupled to the first amplifier and configured to output a first signal based on the first control signal, the first signal having a sensor frequency. The device can also have a first switched-capacitor resistor operably coupled to the first VCO and to the first amplifier, the first switched-capacitor resistor configured to receive and be controlled by the sensor frequency. The device can also have a sensor counter operably coupled to the first VCO and configured produce a sensor count based on the sensor frequency. The device can also have a register configured provide a digital output proportional to the input voltage based on the sensor count.

    摘要翻译： 公开了一种用于模数转换的装置和方法。 该装置可以具有可操作以接收输入电压并输出第一控制信号的第一放大器。 该器件还可以具有可操作地耦合到第一放大器并被配置为基于第一控制信号输出第一信号的第一压控振荡器（VCO），第一信号具有传感器频率。 该器件还可以具有可操作地耦合到第一VCO和第一放大器的第一开关电容器电阻器，第一开关电容器电阻器被配置为接收并由传感器频率控制。 该装置还可以具有可操作地耦合到第一VCO的传感器计数器，并且被配置产生基于传感器频率的传感器计数。 该器件还可以配置寄存器，提供与输入电压成比例的数字输出，该输入电压基于传感器计数。

    Level shifter applicable to low voltage domain to high voltage domain conversion
    6.
    发明授权
    Level shifter applicable to low voltage domain to high voltage domain conversion 有权

    公开(公告)号：US09800246B2

    公开(公告)日：2017-10-24

    申请号：US14859030

    申请日：2015-09-18

    申请人： QUALCOMM Incorporated

    发明人： Masoud Roham ,  Yanjie Meng

    IPC分类号： H03L5/00 ,  H03K19/0185 ,  H03K3/356

    CPC分类号： H03K19/018521 ,  H03K3/35613 ,  H03K3/356182

    摘要： A level shifter includes a latch circuit having a first FET and a second FET; an input circuit having a third FET and a fourth FET, the gates of the first and second FETs being coupled to the drains of the fourth and third FETs, respectively; a first resistive device (resistor, diode-connected FET) coupled between and in series with the first and third FETs between a first voltage rail and a second voltage rail; and a second resistive device (resistor, diode-connected FET) coupled between and in series with the second and fourth FETs between the first and second voltage rails. The gates of the third and fourth FETs are configured to receive a first set of complementary voltages, and a second set of complementary voltages are configured to be generated at the gates of the first and second FETs, respectively. The second set of complementary voltages are based on the first set of complementary voltages.

    Low-power voltage regulator with fast transient response
    7.
    发明授权
    Low-power voltage regulator with fast transient response 有权

    公开(公告)号：US11480985B2

    公开(公告)日：2022-10-25

    申请号：US17154865

    申请日：2021-01-21

    申请人： QUALCOMM Incorporated

    发明人： Xiaopeng Zhong ,  Masoud Roham

    IPC分类号： G05F1/575 ,  G05F1/46 ,  G05F1/565 ,  G05F1/445 ,  G05F3/26

    摘要： In certain aspects, a voltage regulator includes a pass device coupled between an input of the voltage regulator and an output of the voltage regulator. The voltage regulator also includes an amplifying circuit having a first input, a second input, and an output, wherein the first input is configured to receive a reference voltage, the second input is coupled to the output of the voltage regulator via a feedback path, and the output of the amplifying circuit is coupled to a gate of the pass device. The voltage regulator further includes a first current source coupled between a supply rail and the amplifying circuit, and a capacitor coupled between the first current source and the output of the voltage regulator.

    Low voltage, highly accurate current mirror
    9.
    发明授权
    Low voltage, highly accurate current mirror 有权

    公开(公告)号：US09898028B2

    公开(公告)日：2018-02-20

    申请号：US14755435

    申请日：2015-06-30

    申请人： QUALCOMM Incorporated

    发明人： Masoud Roham ,  Liang Dai

    IPC分类号： G05F1/10 ,  G05F3/26 ,  G01R19/00 ,  H03F3/347 ,  H03F3/50

    CPC分类号： G05F3/262 ,  G01R19/0092 ,  H03F3/347 ,  H03F3/505 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2200/474 ,  H03F2200/91

    摘要： Certain aspects of the present disclosure generally relate to a low voltage, accurate current mirror, which may be used for distributed sensing of a remote current in an integrated circuit (IC). One example current mirror typically includes a first pair of transistors, a second pair of transistors in cascode with the first pair of transistors, a switching network coupled to the second pair of transistors, and a third pair of transistors coupled to the switching network. An input node between the first and second pairs of transistors may be configured to receive an input current for the current mirror, and an output node at the first pair of transistors may be configured to sink an output current for the current mirror, proportional to the input current. This current mirror architecture offers a hybrid low-voltage/high-voltage solution, tolerates low input voltages, provides high output impedance, and offers low area and power consumption.