公开(公告)号：US20170085265A1

公开(公告)日：2017-03-23

申请号：US14859030

申请日：2015-09-18

申请人： QUALCOMM Incorporated

发明人： Masoud Roham ,  Yanjie Meng

IPC分类号： H03K19/0185

CPC分类号： H03K19/018521 ,  H03K3/35613 ,  H03K3/356182

摘要： A level shifter includes a latch circuit having a first FET and a second FET; an input circuit having a third FET and a fourth FET, the gates of the first and second FETs being coupled to the drains of the fourth and third FETs, respectively; a first resistive device (resistor, diode-connected FET) coupled between and in series with the first and third FETs between a first voltage rail and a second voltage rail; and a second resistive device (resistor, diode-connected FET) coupled between and in series with the second and fourth FETs between the first and second voltage rails. The gates of the third and fourth FETs are configured to receive a first set of complementary voltages, and a second set of complementary voltages are configured to be generated at the gates of the first and second FETs, respectively. The second set of complementary voltages are based on the first set of complementary voltages.

公开(公告)号：US09800246B2

公开(公告)日：2017-10-24

申请号：US14859030

申请日：2015-09-18

申请人： QUALCOMM Incorporated

发明人： Masoud Roham ,  Yanjie Meng

IPC分类号： H03L5/00 ,  H03K19/0185 ,  H03K3/356

CPC分类号： H03K19/018521 ,  H03K3/35613 ,  H03K3/356182

摘要： A level shifter includes a latch circuit having a first FET and a second FET; an input circuit having a third FET and a fourth FET, the gates of the first and second FETs being coupled to the drains of the fourth and third FETs, respectively; a first resistive device (resistor, diode-connected FET) coupled between and in series with the first and third FETs between a first voltage rail and a second voltage rail; and a second resistive device (resistor, diode-connected FET) coupled between and in series with the second and fourth FETs between the first and second voltage rails. The gates of the third and fourth FETs are configured to receive a first set of complementary voltages, and a second set of complementary voltages are configured to be generated at the gates of the first and second FETs, respectively. The second set of complementary voltages are based on the first set of complementary voltages.