公开(公告)号：US20250096810A1

公开(公告)日：2025-03-20

申请号：US18470309

申请日：2023-09-19

Applicant: QUALCOMM Incorporated

Inventor： Igor GUTMAN ,  Elias DAGHER ,  Hua WANG ,  Behnam SEDIGHI ,  Seyed Arash MIRHAJ ,  Tao LUO

IPC: H03M1/06 ,  G06N3/08 ,  H03M1/12

Abstract: A training signal generator for forming an input signal for an ADC-under-test includes a one-bit DAC and an analog low-pass filter. The one-bit DAC converts a binary sequence into a DAC output signal that is then filtered by the analog low-pass filter to form an ADC input signal. The ADC-under-test converts the ADC input signal into an ADC output signal. A digital low-pass filter converts the binary sequence into a plurality of samples. A digital signal processing system processes the plurality of samples and the ADC output signal to form an estimate of the ADC input signal. An ADC linearizer may then be trained to characterize a non-linear impairment of the ADC-under-test responsive to a comparison of the estimate of the ADC input signal and the ADC output signal.

公开(公告)号：US20190288722A1

公开(公告)日：2019-09-19

申请号：US15962865

申请日：2018-04-25

Applicant: QUALCOMM Incorporated

Inventor： Bhushan Shanti ASURI ,  Krishnaswamy THIAGARAJAN ,  Ashok SWAMINATHAN ,  Shahin MEHDIZAD TALEIE ,  Yen-Wei CHANG ,  Vinod PANIKKATH ,  Sameer Vasantlal VORA ,  Ayush MITTAL ,  Tonmoy BISWAS ,  Sy-Chyuan HWU ,  Zhilong TANG ,  Ibrahim CHAMAS ,  Ping Wing LAI ,  Behnam SEDIGHI ,  Dongwon SEO ,  Nitz SAPUTRA

IPC: H04B1/04 ,  H04B1/00 ,  H04L27/20

Abstract: A communication circuit may include a first pair of digital-to-analog converters (DACs) coupled to an input of a first mixer and configured to generate first baseband signals. The communication circuit may further include a second pair of DACs coupled to an input of a second mixer and configured to generate second baseband signals. The second baseband signals may be shifted in phase relative to the first baseband signals.

公开(公告)号：US20240097698A1

公开(公告)日：2024-03-21

申请号：US17949149

申请日：2022-09-20

Applicant: QUALCOMM Incorporated

Inventor： Behnam SEDIGHI

IPC: H03M1/46 ,  H03M1/18 ,  H03M1/36

CPC classification number: H03M1/462 ,  H03M1/185 ,  H03M1/368

Abstract: Techniques and apparatus for successive approximation register (SAR) analog-to-digital converters (ADCs) with variable resolution. One example SAR ADC is generally configured to convert an analog input signal to a digital output signal, wherein a quantization size of a least significant bit (LSB) associated with the digital output signal is configured to depend on an amplitude of the analog input signal. By utilizing the techniques and apparatus described herein, a SAR ADC may be capable of a higher maximum sampling rate or a lower power dissipation.

公开(公告)号：US20240063765A1

公开(公告)日：2024-02-22

申请号：US17821115

申请日：2022-08-19

Applicant: QUALCOMM Incorporated

Inventor： Behnam SEDIGHI

IPC: H03F3/45 ,  H03M1/12

CPC classification number: H03F3/45183 ,  H03F3/45475 ,  H03M1/122

Abstract: Techniques and apparatus for reducing sensitivity (e.g., less gain variation due to parasitic capacitance) in dynamic amplifiers. One example dynamic amplifier generally includes a pair of differential input transistors, a pair of cross-coupled switches coupled between the pair of differential input transistors and a pair of differential output nodes for the dynamic amplifier, a first pair of switches coupled between the pair of differential input transistors and the pair of differential output nodes, and a second pair of switches coupled between the pair of differential input transistors and the pair of differential output nodes.

公开(公告)号：US20230370085A1

公开(公告)日：2023-11-16

申请号：US17740465

申请日：2022-05-10

Applicant: QUALCOMM Incorporated

Inventor： Lei SUN ,  Aram AKHAVAN ,  Behnam SEDIGHI ,  Tszwing CHOI ,  Henry LAU

IPC: H03M1/80 ,  H01L23/522 ,  H01L49/02 ,  H01G4/38

CPC classification number: H03M1/802 ,  H01L23/5223 ,  H01L28/86 ,  H01G4/38

Abstract: A capacitor device comprises a semiconductor substrate with multiple metal layers above the substrate. a first metal layer has a first plurality of bottom terminals elongated in a first direction, and a first plurality of top terminals, electrically coupled to each other, elongated in the first direction and interleaved with the first plurality of bottom terminals. A second metal layer between the semiconductor substrate and the first metal layer has a second plurality of bottom terminals elongated in the first direction, and a second plurality of top terminals, electrically coupled to each other and the first plurality of top terminals, elongated in the first direction and interleaved with the second plurality of bottom terminals.

公开(公告)号：US20230378970A1

公开(公告)日：2023-11-23

申请号：US17664358

申请日：2022-05-20

Applicant: QUALCOMM Incorporated

Inventor： Igor GUTMAN ,  Behnam SEDIGHI ,  Tao LUO ,  Elias DAGHER ,  Jeremy Darren DUNWORTH

IPC: H03M1/18

CPC classification number: H03M1/188 ,  H03M1/185

Abstract: Certain aspects are directed to an apparatus configured for wireless communication. The apparatus may include a memory comprising instructions, and one or more processors configured to execute the instructions. In some examples, the one or more processors are configured to cause the apparatus to obtain a sample of an analog signal. In some examples, the one or more processors are configured to cause the apparatus to output the sample to an analog-to-digital converter (ADC) via one of at least a first path or a second path based at least in part on whether the sample satisfies a first threshold condition or a second threshold condition.

公开(公告)号：US20210391871A1

公开(公告)日：2021-12-16

申请号：US17337619

申请日：2021-06-03

Applicant: QUALCOMM Incorporated

Inventor： Xilin LIU ,  Nitz SAPUTRA ,  Behnam SEDIGHI ,  Ashok SWAMINATHAN ,  Dongwon SEO

IPC: H03M1/74 ,  G05F3/26 ,  H04B1/04

Abstract: Methods and apparatus for adaptively generating a reference voltage (VREF) for biasing a switch driver and corresponding switch in a digital-to-analog converter (DAC). The adaptive biasing scheme may be capable of tracking process, voltage, and temperature (PVT) of the DAC. An example DAC generally includes a plurality of DAC cells, each DAC cell comprising a current source, a switch coupled in series with the current source, and a switch driver coupled to a control input of the switch, the switch driver being configured to receive power from a first power supply rail referenced to a reference potential node; a regulation circuit comprising a first transistor coupled between the reference potential node for the DAC and the switch driver in at least one of the plurality of DAC cells; and a VREF generation circuit coupled to the regulation circuit and configured to adaptively generate a VREF for the regulation circuit.

公开(公告)号：US20200169266A1

公开(公告)日：2020-05-28

申请号：US16202723

申请日：2018-11-28

Applicant: QUALCOMM Incorporated

Inventor： Shahin MEHDIZAD TALEIE ,  Behnam SEDIGHI ,  Dongwon SEO ,  Parisa MAHMOUDIDARYAN ,  Bhushan Shanti ASURI ,  Sang-June PARK ,  Shrenik PATEL

IPC: H03M1/66

Abstract: Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example system for digital-to-analog conversion generally includes a first digital-to-analog converter (DAC) having an input coupled to an input node of the system and a mixing-mode DAC having an input coupled to an input node of the system. The mixing-mode DAC may include a second DAC and a mixer, an output of the second DAC being coupled to an input of the mixer. The system may also include a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the mixer is coupled to a second input of the combiner.

公开(公告)号：US20180358883A1

公开(公告)日：2018-12-13

申请号：US15710704

申请日：2017-09-20

Applicant: QUALCOMM Incorporated

Inventor： Nitz SAPUTRA ,  Sang Min LEE ,  Dongwon SEO ,  Vinay KUNDUR ,  Behnam SEDIGHI ,  Honghao JI

IPC: H02M1/00 ,  H02J5/00 ,  H02M1/14

CPC classification number: H02M1/00 ,  H02J5/00 ,  H02M1/143 ,  H02M2001/0006 ,  H02M2001/0012

Abstract: A calibrating digital to analog converter (calDAC) architecture uses a low voltage memory to store the digital inputs of calDACs. The calDAC architecture includes a low voltage domain and a high voltage domain coupled to the low voltage domain. The low voltage domain includes a calDAC memory and a finite state machine (FSM). The high voltage domain includes a calDAC core, an interface circuit, and a bias control circuit coupled to the interface circuit. The interface circuit may be provided between the calDAC core and the low voltage domain. The bias control circuit is coupled to the interface circuit to generate a bias voltage for the interface circuit to drive switch transistors of the calDAC core.

公开(公告)号：US20250096750A1

公开(公告)日：2025-03-20

申请号：US18467313

申请日：2023-09-14

Applicant: QUALCOMM Incorporated

Inventor： Zeljko IGNJATOVIC ,  Behnam SEDIGHI

IPC: H03F3/217

Abstract: Certain aspects of the present disclosure generally relate to a voltage-to-time-to-voltage amplifier (VTVA). The VTVA may include: a first input capacitive element selectively coupled to a first input node of the VTVA; a first amplifier having an input coupled to the first input capacitive element; a first current source configured to sink a first discharge current from the first input capacitive element during a first phase through a first switch; and a first output capacitive element coupled to a first output node of the VTVA. In some aspects, the first current source is further configured to sink a second discharge current from the first output capacitive element during a second phase through a second switch, the second switch comprising a control input coupled to an output of the first amplifier; and the first phase is non-overlapping with the second phase.