公开(公告)号：US20240364325A1

公开(公告)日：2024-10-31

申请号：US18307441

申请日：2023-04-26

Applicant: QUALCOMM Incorporated

Inventor： Lei SUN ,  Yongjian TANG ,  Honghao JI

IPC: H03K17/16

CPC classification number: H03K17/162

Abstract: A system includes a bootstrap circuit having an input and an output. The bootstrap circuit includes a boost capacitor having a first terminal and a second terminal, a first transistor coupled between the first terminal of the boost capacitor and the output of the bootstrap circuit, a second transistor, and a third transistor, wherein the second transistor and the third transistor are coupled in series between a gate of the first transistor and the second terminal of the boost capacitor. The system also includes a switch transistor, wherein a gate of the switch transistor is coupled to the output of the bootstrap circuit, and a terminal of the switch transistor is coupled to the input of the bootstrap circuit.

公开(公告)号：US20180358883A1

公开(公告)日：2018-12-13

申请号：US15710704

申请日：2017-09-20

Applicant: QUALCOMM Incorporated

Inventor： Nitz SAPUTRA ,  Sang Min LEE ,  Dongwon SEO ,  Vinay KUNDUR ,  Behnam SEDIGHI ,  Honghao JI

IPC: H02M1/00 ,  H02J5/00 ,  H02M1/14

CPC classification number: H02M1/00 ,  H02J5/00 ,  H02M1/143 ,  H02M2001/0006 ,  H02M2001/0012

Abstract: A calibrating digital to analog converter (calDAC) architecture uses a low voltage memory to store the digital inputs of calDACs. The calDAC architecture includes a low voltage domain and a high voltage domain coupled to the low voltage domain. The low voltage domain includes a calDAC memory and a finite state machine (FSM). The high voltage domain includes a calDAC core, an interface circuit, and a bias control circuit coupled to the interface circuit. The interface circuit may be provided between the calDAC core and the low voltage domain. The bias control circuit is coupled to the interface circuit to generate a bias voltage for the interface circuit to drive switch transistors of the calDAC core.