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公开(公告)号:US20190296755A1
公开(公告)日:2019-09-26
申请号:US15936015
申请日:2018-03-26
Applicant: QUALCOMM Incorporated
Inventor: Seyed Arash MIRHAJ , Masoud ENSAFDARAN , Lei SUN , Dinesh ALLADI
Abstract: Certain aspects of the present disclosure provide methods and apparatus for performing background noise estimation using a circular histogram noise figure (CHNF) in an analog-to-digital converter (ADC) circuit with redundancy. The estimated noise may be used to reduce the noise (e.g., comparator noise) in the ADC circuit. One example ADC circuit generally includes at least one of a comparator or a digital-to-analog converter (DAC) and at least one digital feedback input. The at least one digital feedback input is coupled to the at least one of the comparator or the DAC and is configured to adjust at least one parameter of the at least one of the comparator or the DAC based on at least a portion of an output of the ADC circuit.
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公开(公告)号:US20250015934A1
公开(公告)日:2025-01-09
申请号:US18710586
申请日:2022-01-20
Applicant: QUALCOMM Incorporated
Inventor: Lei SUN , Peng WU , Arun Prasanth BALASUBRAMANIAN , Jason TAN , Yuyi LI , Vaishakh RAO , Sivaram Srivenkata PALAKODETY , Vishal DALMIYA , Mariano IBERICO TORRES , Shailesh MAHESHWARI , Tom CHIN
IPC: H04L1/1829 , H04L47/32 , H04L47/34
Abstract: Aspects of the present disclosure provide mechanisms for fast hyper frame number (HFN) resynchronization of Packet Data Convergence Protocol (PDCP) Protocol Data Units (PDUs). A wireless communication device (e.g., a PDCP entity at a wireless communication device) can calculate a current PDCP count of a current PDCP PDU of a plurality of PDCP PDUs received from a radio link control (RLC) sublayer based on a PDCP sequence number (SN) of the current PDCP PDU and an HFN of a first missing PDCP PDU after a successfully received PDCP PDU. The PDCP count may be calculated using the HFN of the first missing PDCP PDU in response to a gap between the PDCP count of the first missing PDCP PDU and the actual PDCP count of the current PDCP PDU being greater than a PDCP window size.
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公开(公告)号:US20240364325A1
公开(公告)日:2024-10-31
申请号:US18307441
申请日:2023-04-26
Applicant: QUALCOMM Incorporated
Inventor: Lei SUN , Yongjian TANG , Honghao JI
IPC: H03K17/16
CPC classification number: H03K17/162
Abstract: A system includes a bootstrap circuit having an input and an output. The bootstrap circuit includes a boost capacitor having a first terminal and a second terminal, a first transistor coupled between the first terminal of the boost capacitor and the output of the bootstrap circuit, a second transistor, and a third transistor, wherein the second transistor and the third transistor are coupled in series between a gate of the first transistor and the second terminal of the boost capacitor. The system also includes a switch transistor, wherein a gate of the switch transistor is coupled to the output of the bootstrap circuit, and a terminal of the switch transistor is coupled to the input of the bootstrap circuit.
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公开(公告)号:US20240305296A1
公开(公告)日:2024-09-12
申请号:US18181026
申请日:2023-03-09
Applicant: QUALCOMM Incorporated
Inventor: Lei SUN , Elias DAGHER , Dinesh Jagannath ALLADI
IPC: H03K19/003 , H03K17/06 , H03K17/687 , H03K19/017
CPC classification number: H03K19/00361 , H03K17/063 , H03K17/6871 , H03K19/01735
Abstract: A system includes a switch transistor, and a bootstrap circuit having an input and an output, wherein the output of the bootstrap circuit is coupled to a gate of the switch transistor. The system also includes a first buffer having an input and an output, wherein the output of the first buffer is coupled to a terminal of the switch transistor. The system further includes a second buffer having an input and an output, wherein the input of the second buffer is coupled to the input of the first buffer, and the output of the second buffer is coupled to the input of the bootstrap circuit.
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公开(公告)号:US20230370085A1
公开(公告)日:2023-11-16
申请号:US17740465
申请日:2022-05-10
Applicant: QUALCOMM Incorporated
Inventor: Lei SUN , Aram AKHAVAN , Behnam SEDIGHI , Tszwing CHOI , Henry LAU
IPC: H03M1/80 , H01L23/522 , H01L49/02 , H01G4/38
CPC classification number: H03M1/802 , H01L23/5223 , H01L28/86 , H01G4/38
Abstract: A capacitor device comprises a semiconductor substrate with multiple metal layers above the substrate. a first metal layer has a first plurality of bottom terminals elongated in a first direction, and a first plurality of top terminals, electrically coupled to each other, elongated in the first direction and interleaved with the first plurality of bottom terminals. A second metal layer between the semiconductor substrate and the first metal layer has a second plurality of bottom terminals elongated in the first direction, and a second plurality of top terminals, electrically coupled to each other and the first plurality of top terminals, elongated in the first direction and interleaved with the second plurality of bottom terminals.
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公开(公告)号:US20230098404A1
公开(公告)日:2023-03-30
申请号:US17486745
申请日:2021-09-27
Applicant: QUALCOMM Incorporated
Inventor: Cheng TAN , Lei SUN , Sean Vincent MASCHUE , Bruce Charles FISCHER, JR. , Brian FRENCH
Abstract: Certain aspects of the present disclosure provide techniques for determining a cable loss associated with a transmission cable of an apparatus. An example method includes sending, to a radio modem of the apparatus, a request for the radio modem to use a target power when sending one or more signals to the signal compensator device for determining a cable loss associated with a transmission cable communicatively coupling the radio modem with the signal compensator device, receiving, at a signal compensator device of the apparatus, the one or more signals from the radio modem sent using the target power, and determining the cable loss associated with the transmission cable based on the one or more signals.
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公开(公告)号:US20230046277A1
公开(公告)日:2023-02-16
申请号:US17403683
申请日:2021-08-16
Applicant: QUALCOMM Incorporated
Inventor: Aram AKHAVAN , Kentaro YAMAMOTO , Lei SUN , Ganesh KIRAN
Abstract: Techniques and apparatus for output common-mode control of dynamic amplifiers, as well as analog-to-digital converters (ADCs) and other circuits implemented with such dynamic amplifiers. One example amplifier circuit includes a dynamic amplifier and a current source. The dynamic amplifier generally includes differential inputs, differential outputs, transconductance elements coupled to the differential inputs, a first set of capacitive elements coupled to the differential outputs, and a control input for controlling a time length of amplification for the dynamic amplifier. The current source is configured to generate an output current such that portions of the output current are selectively applied to the differential outputs of the dynamic amplifier during at least a portion of the time length of amplification.
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