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1.发明授权Amplifiers with inductive degeneration and configurable gain and input matching 有权具有电感退化和可配置增益和输入匹配的放大器公开(公告)号：US09106185B2
公开(公告)日：2015-08-11
申请号：US13794110
申请日：2013-03-11
Applicant: QUALCOMM Incorporated
Inventor： Ahmed A Youssef , Sherif Abdelhalem , Ehab A Abdel Ghany , Li-Chung Chang
CPC classification number: H03F1/223 , H03F1/08 , H03F1/56 , H03F3/189 , H03F3/45179 , H03F2200/492 , H03G1/0023
Abstract: Amplifiers with inductive degeneration and configurable gain and input matching are disclosed. In an exemplary design, an apparatus includes a gain transistor, an inductor, and an input matching circuit for an amplifier. The gain transistor has a variable gain determined based on its bias current. The inductor is coupled between the gain transistor and circuit ground. The input matching circuit is selectively coupled to the gain transistor based on the variable gain of the gain transistor. For example, the input matching circuit may be coupled to the gain transistor in a low-gain mode and decoupled from the gain transistor in the high-gain mode. In an exemplary design, the input matching circuit includes a resistor, a capacitor, and a second transistor coupled in series. The resistor is used for input matching of the amplifier. The second transistor couples or decouples the resistor to or from the gain transistor.
Abstract translation: 公开了具有感应退化和可配置增益和输入匹配的放大器。 在示例性设计中，装置包括用于放大器的增益晶体管，电感器和输入匹配电路。 增益晶体管具有基于其偏置电流确定的可变增益。 电感器耦合在增益晶体管和电路接地之间。 基于增益晶体管的可变增益，输入匹配电路选择性地耦合到增益晶体管。 例如，输入匹配电路可以以低增益模式耦合到增益晶体管，并在高增益模式中与增益晶体管去耦。 在示例性设计中，输入匹配电路包括串联耦合的电阻器，电容器和第二晶体管。 该电阻用于放大器的输入匹配。 第二个晶体管将电阻器耦合或去耦合增益晶体管。
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Patent Agency Ranking
公开(公告)号：US09800273B1
公开(公告)日：2017-10-24
申请号：US15446847
申请日：2017-03-01
Applicant: QUALCOMM Incorporated
Inventor： Sherif Abdelhalem , Bassel Hanafi , Hasnain Lakdawala
CPC classification number: H04B1/0458 , H03F3/193 , H03F3/195 , H03F3/245 , H03F3/3022 , H03F3/68 , H03F3/72 , H03F2200/111 , H03F2200/165 , H03F2200/294 , H03F2200/357 , H03F2200/451 , H04B1/0475
Abstract: A device and method for amplifying signals is provided. The device can have an input to receive an input signal having a first desired signal on a first carrier, a second desired signal on a second carrier, and one or more interfering signals. The device can have a first carrier aggregation (CA) chain for use with the first desired signal and a second CA chain for use with the second desired signal. The first and second CA chains can be coupled to the input. The first and second CA chains can have a plurality of transconductance stages. Each of the transconductance stages can be configured as a high impedance stage or a low impedance stage. The transconductance stages can be selectively activated to incrementally adjust the transconductance, and therefore the input impedance, of each of the CA chains.
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3.发明申请AMPLIFIERS WITH INDUCTIVE DEGENERATION AND CONFIGURABLE GAIN AND INPUT MATCHING 有权具有电感衰减和可配置增益和输入匹配的放大器公开(公告)号：US20140253242A1
公开(公告)日：2014-09-11
申请号：US13794110
申请日：2013-03-11
Applicant: QUALCOMM INCORPORATED
Inventor： Ahmed A. Youssef , Sherif Abdelhalem , Ehab A. Abdel Ghany , Li-Chung Chang
IPC: H03G3/30
CPC classification number: H03F1/223 , H03F1/08 , H03F1/56 , H03F3/189 , H03F3/45179 , H03F2200/492 , H03G1/0023
Abstract: Amplifiers with inductive degeneration and configurable gain and input matching are disclosed. In an exemplary design, an apparatus includes a gain transistor, an inductor, and an input matching circuit for an amplifier. The gain transistor has a variable gain determined based on its bias current. The inductor is coupled between the gain transistor and circuit ground. The input matching circuit is selectively coupled to the gain transistor based on the variable gain of the gain transistor. For example, the input matching circuit may be coupled to the gain transistor in a low-gain mode and decoupled from the gain transistor in the high-gain mode. In an exemplary design, the input matching circuit includes a resistor, a capacitor, and a second transistor coupled in series. The resistor is used for input matching of the amplifier. The second transistor couples or decouples the resistor to or from the gain transistor.
Abstract translation: 公开了具有感应退化和可配置增益和输入匹配的放大器。 在示例性设计中，装置包括用于放大器的增益晶体管，电感器和输入匹配电路。 增益晶体管具有基于其偏置电流确定的可变增益。 电感器耦合在增益晶体管和电路接地之间。 基于增益晶体管的可变增益，输入匹配电路选择性地耦合到增益晶体管。 例如，输入匹配电路可以以低增益模式耦合到增益晶体管，并在高增益模式中与增益晶体管去耦。 在示例性设计中，输入匹配电路包括串联耦合的电阻器，电容器和第二晶体管。 该电阻用于放大器的输入匹配。 第二个晶体管将电阻器耦合或去耦合增益晶体管。
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公开(公告)号：US08975968B2
公开(公告)日：2015-03-10
申请号：US13750878
申请日：2013-01-25
Applicant: QUALCOMM Incorporated
Inventor： Sherif Abdelhalem , William James Biederman, III
CPC classification number: H03F1/0205 , H03F1/0261 , H03F1/0277 , H03F1/22 , H03F1/223 , H03F1/523 , H03F3/193 , H03F3/195 , H03F3/211 , H03F3/22 , H03F3/245 , H03F3/68 , H03F3/72 , H03F2200/108 , H03F2200/294 , H03F2200/426 , H03F2200/541 , H03F2203/21142 , H03F2203/7206
Abstract: Amplifiers with improved isolation are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes an amplifier having a gain transistor, first and second cascode transistors, and a shunt transistor. The gain transistor receives an input signal and provides an amplified signal. The first cascode transistor is coupled between the gain transistor and an intermediate node and receives the amplified signal. The second cascode transistor is coupled between the intermediate node and an output node and provides an output signal. The shunt transistor is coupled between the intermediate node and circuit ground. The first and second cascode transistors are enabled to provide the output signal. The shunt transistor is (i) disabled when the cascode transistors are enabled and (ii) enabled to short the intermediate node to circuit ground when the cascode transistors are disabled.
Abstract translation: 公开了具有改进的隔离的放大器。 在示例性设计中，装置（例如，无线装置，集成电路等）包括具有增益晶体管，第一和第二共源共栅晶体管以及分流晶体管的放大器。 增益晶体管接收输入信号并提供放大信号。 第一共源共栅晶体管耦合在增益晶体管和中间节点之间，并接收放大的信号。 第二共源共栅晶体管耦合在中间节点和输出节点之间并提供输出信号。 分流晶体管耦合在中间节点和电路接地之间。 使第一和第二共源共栅晶体管能够提供输出信号。 分流晶体管是（i）当共源共栅晶体管使能时被禁止，（ii）当共源共栅晶体管被禁用时，能够将中间节点短路到电路接地。
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公开(公告)号：US20140210554A1
公开(公告)日：2014-07-31
申请号：US13750878
申请日：2013-01-25
Applicant: QUALCOMM INCORPORATED
Inventor： Sherif Abdelhalem , William James Biederman, III
CPC classification number: H03F1/0205 , H03F1/0261 , H03F1/0277 , H03F1/22 , H03F1/223 , H03F1/523 , H03F3/193 , H03F3/195 , H03F3/211 , H03F3/22 , H03F3/245 , H03F3/68 , H03F3/72 , H03F2200/108 , H03F2200/294 , H03F2200/426 , H03F2200/541 , H03F2203/21142 , H03F2203/7206
Abstract: Amplifiers with improved isolation are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes an amplifier having a gain transistor, first and second cascode transistors, and a shunt transistor. The gain transistor receives an input signal and provides an amplified signal. The first cascode transistor is coupled between the gain transistor and an intermediate node and receives the amplified signal. The second cascode transistor is coupled between the intermediate node and an output node and provides an output signal. The shunt transistor is coupled between the intermediate node and circuit ground. The first and second cascode transistors are enabled to provide the output signal. The shunt transistor is (i) disabled when the cascode transistors are enabled and (ii) enabled to short the intermediate node to circuit ground when the cascode transistors are disabled.
Abstract translation: 公开了具有改进的隔离的放大器。 在示例性设计中，装置（例如，无线装置，集成电路等）包括具有增益晶体管，第一和第二共源共栅晶体管以及分流晶体管的放大器。 增益晶体管接收输入信号并提供放大信号。 第一共源共栅晶体管耦合在增益晶体管和中间节点之间，并接收放大的信号。 第二共源共栅晶体管耦合在中间节点和输出节点之间并提供输出信号。 分流晶体管耦合在中间节点和电路接地之间。 使第一和第二共源共栅晶体管能够提供输出信号。 分流晶体管是（i）当共源共栅晶体管使能时被禁止，（ii）当共源共栅晶体管被禁用时，能够将中间节点短路到电路接地。
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公开(公告)号：US10033340B1
公开(公告)日：2018-07-24
申请号：US15400078
申请日：2017-01-06
Applicant: QUALCOMM Incorporated
Inventor： Bassel Hanafi , Sherif Abdelhalem , Hasnain Lakdawala
Abstract: Certain aspects of the present disclosure generally relate to a multi-output amplifier implemented using a capacitive attenuator. For example, the multi-output amplifier generally includes a first capacitive attenuator coupled to an input node of the multi-output amplifier. In certain aspects, the multi-output amplifier also includes a first amplification stage having an input coupled to a tap node of the first capacitive attenuator and an output coupled to a first output node of the multi-output amplifier, and a second amplification stage having an output coupled to a second output node of the multi-output amplifier. For certain aspects, the multi-output amplifier includes a second capacitive attenuator coupled to the input node of the multi-output amplifier, and the second amplification stage may have an input coupled to a tap node of the second capacitive attenuator.
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