公开(公告)号：US20250021478A1

公开(公告)日：2025-01-16

申请号：US18349206

申请日：2023-07-10

Applicant: QUALCOMM Incorporated

Inventor： Manish GARG ,  Pratibind Kumar JHA ,  Prakhar SRIVASTAVA ,  Santhosh Reddy AKAVARAM

IPC: G06F12/02

Abstract: Methods that may be performed by a host controller and a memory controller of a computing device. The method synchronizes memory tables between the storage device and a host device by modifying an indicator in a first memory table on the storage device in response to a change in a memory mapping, the first memory table mapping logical addresses to physical addresses of memory on the storage device, the indicator identifying one or more address mapping changes of the first memory table, notifying the host device that the first memory table has been modified, and transmitting to the host device at least a portion of the first memory table including the one or more address mapping changes. The storage device processes memory requests from the host device based on one or more addresses affected by the one or more address mapping changes.

公开(公告)号：US20240202140A1

公开(公告)日：2024-06-20

申请号：US18081396

申请日：2022-12-14

Applicant: QUALCOMM Incorporated

Inventor： Santhosh Reddy AKAVARAM ,  Prakhar SRIVASTAVA ,  Rajendra Varma PUSAPATI ,  Ravindranath DODDI ,  Yogananda Rao CHILLARIGA

IPC: G06F13/12

CPC classification number: G06F13/126 ,  G06F2213/0026

Abstract: Aspects relate to lane failure recovery for a data link having multiple lanes labeled in a contiguous sequence. In one aspect, a failure of a failed lane of the data link is detected. Working lanes of the data link are then detected. A set of contiguous working lanes of the data link are selected, and an operational link as including the selected set of contiguous working lanes is defined. A start address of the operational link is identified and stored in a configuration register. Data traffic is transmitted on the operational link.

公开(公告)号：US20250103499A1

公开(公告)日：2025-03-27

申请号：US18472642

申请日：2023-09-22

Applicant: QUALCOMM Incorporated

Inventor： Santhosh Reddy AKAVARAM ,  Chintalapati BHARATH SAI VARMA ,  Prakhar SRIVASTAVA ,  Hung VUONG ,  Ravi Kumar SEPURI

IPC: G06F12/084 ,  G06F12/02

Abstract: A host device includes a host controller interface (HCI) configured to be coupled to a flash memory device and configured to receive a notification from the flash memory device that a performance threshold register value has been exceeded while the flash memory device is configured to use a shared write buffer. The HCI is also configured to, in response to receiving the notification, perform a remedial action that includes reassigning a portion of a first logical unit (LU).

公开(公告)号：US20240411481A1

公开(公告)日：2024-12-12

申请号：US18530074

申请日：2023-12-05

Applicant: QUALCOMM Incorporated

Inventor： Chintalapati BHARATH SAI VARMA ,  Santhosh Reddy AKAVARAM ,  Sai Naresh GAJAPAKA ,  Hung VUONG ,  Radhakrishna MUGADA ,  Prakhar SRIVASTAVA ,  Vamsi Krishna SAMBANGI

IPC: G06F3/06

Abstract: Methods that may be performed by a universal flash storage (UFS) system of a computing device for optimizing usage of a shared write booster buffer to extend lifetime. The method may include writing data to a flash storage device including a plurality of logical units of memory by receiving a command identifying a logical unit among the plurality of logical units to store data and data for storage in the identified logical unit, obtaining information indicating a memory write type for the identified logical unit, and writing the received data to either a shared write booster buffer before writing to the identified logical unit of device storage or directly to the identified logical unit of device storage based on the obtained memory write type

公开(公告)号：US20240143434A1

公开(公告)日：2024-05-02

申请号：US17976468

申请日：2022-10-28

Applicant: QUALCOMM Incorporated

Inventor： Santhosh Reddy AKAVARAM ,  Prakhar SRIVASTAVA ,  Sai Sreeja MUKKA ,  Yogananda Rao CHILLARIGA ,  Ravindranath DODDI

IPC: G06F11/07 ,  G06F13/40

CPC classification number: G06F11/0793 ,  G06F11/0745 ,  G06F13/4059 ,  G06F2213/0026

Abstract: Aspects of the disclosure provide techniques for retransmitting transaction layer packets (TLPs) for which a negative acknowledgment (NACK) is received without retransmitting previously transmitted TLPs that are correctly received, yet out-of-sequence, by a receiver. A receiver (e.g., a receiving link partner) can provide a transmitter (e.g., a transmitting link partner) with a NACK that includes a starting sequence number (SSN) and an ending sequence number (ESN), which can notify the transmitter about the packets for retransmission and/or packets that can be purged from a transmit buffer of the transmitter.

公开(公告)号：US20230325342A1

公开(公告)日：2023-10-12

申请号：US17715792

申请日：2022-04-07

Applicant: QUALCOMM Incorporated

Inventor： Prakhar SRIVASTAVA ,  Ravindranath DODDI ,  Santhosh Reddy AKAVARAM

IPC: G06F13/42 ,  G06F13/40 ,  G06F1/3234 ,  G06F1/08

CPC classification number: G06F13/4221 ,  G06F1/08 ,  G06F1/3253 ,  G06F13/4072

Abstract: Aspects relate to power management for a peripheral component interconnect. Transmit traffic activity may be monitored for a peripheral component interconnect express (PCIe) link. Receive traffic activity may also be monitored for the link A first power of transmit lines of the link is managed as a transmit group in accordance with the transmit traffic activity. A second power of the receive lines of the link are managed as a receive group in accordance with the receive traffic activity. The first power of the transmit lines is managed independently of the second power of the receive lines.

公开(公告)号：US20250094268A1

公开(公告)日：2025-03-20

申请号：US18468479

申请日：2023-09-15

Applicant: QUALCOMM Incorporated

Inventor： Santhosh Reddy AKAVARAM ,  Prakhar SRIVASTAVA ,  Sridhar ANUMALA ,  Chintalapati BHARATH SAI VARMA

IPC: G06F11/07 ,  G06F13/42

Abstract: Various embodiments include methods and devices for efficiently recovering from errors that occur in part but not all of a universal chiplet interconnect express (UCIe) link for chiplets of a computing device. Various embodiments may include identifying a first part of a UCIe link in which an error has occurred, and training the first part of the UCIe link in which the error has occurred while maintaining active a second part of the UCIe link in which no error has occurred.

公开(公告)号：US20250013572A1

公开(公告)日：2025-01-09

申请号：US18347359

申请日：2023-07-05

Applicant: QUALCOMM Incorporated

Inventor： Sonali JABREVA ,  Sridhar ANUMALA ,  Santhosh Reddy AKAVARAM ,  Prakhar SRIVASTAVA ,  Manish GARG

IPC: G06F12/0855 ,  G06F12/02

Abstract: Aspects relate to interrupting memory access during background operations of a memory device. In one example, a host for a memory device includes background operation circuitry configured to permit a background operation by a memory device. The host is coupled to the memory device through a bus. The host receives an operation completed notification from the memory device to indicate that the memory device has completed performing the background operation. Memory access command circuitry is configured to receive a memory access command. The memory access command concerns reading or writing data to the memory device coupled to the host. The memory access command circuitry initiates a wait at the host for the memory access command, and sends the memory access command to the memory device in response to receiving the operation completed notification.

公开(公告)号：US20240427709A1

公开(公告)日：2024-12-26

申请号：US18338653

申请日：2023-06-21

Applicant: QUALCOMM INCORPORATED

Inventor： Santhosh Reddy AKAVARAM ,  Prakhar SRIVASTAVA ,  Sridhar ANUMALA ,  Ramacharan SUNDARARAMAN ,  Sonali JABREVA ,  Khushboo KUMARI ,  Sanjay VERDU

IPC: G06F13/16

Abstract: Methods and apparatuses are provided to reduce latencies associated with state transitions in die-to-die interconnect architectures. In one example, a physical layer of a die detects a first event indicating a transition to a lower power state. In response to the first event, the physical layer transitions to a lower power state where one or more clock configuration values are read from registers and stored in memory. The physical layer then detects a second event indicating a transition to an active state. In response to the second event, the physical layer reads the clock configuration values from the memory, and writes the clock configuration values to the registers. The physical layer then transitions to a power stabilization state, and remains in the power stabilization state for an amount of time to allow clocks to stabilize. The physical layer then transitions to a training state.

公开(公告)号：US20240111700A1

公开(公告)日：2024-04-04

申请号：US17960050

申请日：2022-10-04

Applicant: QUALCOMM Incorporated

Inventor： Prakhar SRIVASTAVA ,  Santhosh Reddy AKAVARAM ,  Ravindranath DODDI ,  Ravi Kumar SEPURI

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4031 ,  G06F13/4221 ,  G06F2213/0026

Abstract: Aspects relate to link speed for a peripheral component interconnect. In one aspect, an apparatus includes an interface circuit configured to provide an interface with a multiple lane data link, the data link having a first set of lanes in an active state and a second set of lanes in an idle state and a controller. The controller is configured to receive a request at the controller to change a data rate of the data link to a requested data rate, change the second set of lanes from an idle state to an active state, train the second set of lanes to the requested data rate, transfer data traffic from the first set of lanes to the second set of lanes after the training, and transmit the data traffic on the second set of lanes.