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公开(公告)号：US20240402923A1
公开(公告)日：2024-12-05
申请号：US18327691
申请日：2023-06-01
Applicant: QUALCOMM Incorporated
Inventor： Santhosh Reddy AKAVARAM , Prakhar SRIVASTAVA , Sridhar ANUMALA , Hung VUONG , Sonali JABREVA , Khushboo KUMARI
IPC: G06F3/06
Abstract: Aspects of the present disclosure are directed to techniques and procedures for storing data in a data storage device that uses nonvolatile memory (NVM) to store data. The NVM can be organized into logical units that are assigned respective logical unit numbers. The data storage device can report to a host the amount of spare blocks needed for one or more logical units (LUs), and then the host can relinquish some memory blocks to be reallocated as spare blocks. The data storage device can implement a spare block resource management policy per LU and allocate a predetermined amount of spare blocks per LU. The data storage device can implement a spare block resource management policy per memory type and allocate a predetermined amount of spare blocks for LUs with the same memory type.
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公开(公告)号：US20180137896A1
公开(公告)日：2018-05-17
申请号：US15782833
申请日：2017-10-12
Applicant: QUALCOMM Incorporated
Inventor： Hyunsuk SHIN , David TEB , Hung VUONG , Venkatakrishnan GOPALAKRISHNAN
CPC classification number: G11C7/1003 , G06F3/0619 , G06F12/0246 , G06F13/102 , G06F13/1668 , G06F13/4247
Abstract: In conventional systems with a plurality of UFS devices daisy-chained to a UFS host, a UFS device driver must be able to differentiate among the links, and send either link control messages or data/management (D/M) messages to a UFS host controller. This can make force the UFS device driver to be complicated and error prone. To address this issue, a host controller can provide a uniform view of a plurality of daisy-chained devices to a device driver of a host. For example, the host controller can be such that from the perspective of the device driver, each device can appear to be a point-to-point connected device. This can allow the device driver to use a same set of link control messages to control the links. In this way, the device driver can be simplified and thus less error prone.
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公开(公告)号：US20170365352A1
公开(公告)日：2017-12-21
申请号：US15615827
申请日：2017-06-06
Applicant: QUALCOMM Incorporated
Inventor： Hyunsuk SHIN , Robert HARDACKER , Hung VUONG
CPC classification number: G11C16/3431 , G06F12/0246 , G11C16/3418
Abstract: Systems and method for a host-driven data refresh of a Flash memory include registers provided in the Flash memory for storing various settings related to refresh operations, such as, when to start/stop refreshing, target partitions in the memory, target start/end address ranges for refreshing, refresh algorithms, refresh rate requirements, etc. A host can control the various settings for start/stop refreshing, target partitions in the memory, target start/end address ranges for refreshing, refresh algorithms, through the corresponding registers; and the Flash memory can control various values related to refresh rate requirements through corresponding registers. In this manner, a standard platform or interface is provided within the Flash memory for refresh operations thereof.
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公开(公告)号：US20190121540A1
公开(公告)日：2019-04-25
申请号：US15789903
申请日：2017-10-20
Applicant: QUALCOMM Incorporated
Inventor： Hyunsuk SHIN , David TEB , Hung VUONG
Abstract: In a conventional system with a UFS device connected to a UFS host implementing HPB features, a UFS driver software generates commands, e.g., read and write commands, for the UFS device to perform. The commands include both physical and logical addresses of the UFS device. Typically, the UFS driver software is software based. Therefore, there is much overhead associated with implementing the HPB. To address this issue, it is proposed to enable a hardware based host controller to perform operations related to the HPB. In this way, the performance of a system may be improved.
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公开(公告)号：US20190066811A1
公开(公告)日：2019-02-28
申请号：US16175745
申请日：2018-10-30
Applicant: QUALCOMM Incorporated
Inventor： Hyunsuk SHIN , Robert HARDACKER , Hung VUONG
CPC classification number: G11C16/3431 , G06F12/0246 , G11C16/3418
Abstract: Systems and method for a host-driven data refresh of a Flash memory include registers provided in the Flash memory for storing various settings related to refresh operations, such as, when to start/stop refreshing, target partitions in the memory, target start/end address ranges for refreshing, refresh algorithms, refresh rate requirements, etc. A host can control the various settings for start/stop refreshing, target partitions in the memory, target start/end address ranges for refreshing, refresh algorithms, through the corresponding registers; and the Flash memory can control various values related to refresh rate requirements through corresponding registers. In this manner, a standard platform or interface is provided within the Flash memory for refresh operations thereof.
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Patent Agency Ranking
公开(公告)号：US20250044945A1
公开(公告)日：2025-02-06
申请号：US18365700
申请日：2023-08-04
Applicant: QUALCOMM Incorporated
Inventor： Pratibind Kumar JHA , Manish GARG , Prakhar SRIVASTAVA , Santhosh Reddy AKAVARAM , Hung VUONG , Abhishek GHOSH , Shubham KANWAL
IPC: G06F3/06 , G06F12/0802 , G06F12/1009
Abstract: A host device includes system memory that includes a logical-to-physical (L2P) cache and a second cache. The host device also includes a host controller interface (HCI) configured to be coupled to a flash memory device. The HCI is configured to determine that a particular region of a L2P address mapping table is to be removed from the L2P cache. The L2P address mapping table is configured to include mappings between logical memory addresses and physical memory addresses of the flash memory device. The HCI is also configured to identify a particular sub-region of the particular region having an access metric that satisfies a retention criterion. The HCI is further configured to store the particular sub-region into the second cache. The HCI is also configured to remove the particular region from the L2P cache.
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公开(公告)号：US20190034106A1
公开(公告)日：2019-01-31
申请号：US16030841
申请日：2018-07-09
Applicant: QUALCOMM Incorporated
Inventor： Hyunsuk SHIN , Todd Christopher REYNOLDS , Hung VUONG
Abstract: Systems and method are directed to Universal Flash Storage (UFS) memory system configured to support deep power-down modes wherein the UFS memory system is not required to be responsive to commands received from a host device coupled to the UFS memory system. Correspondingly, in the deep power-down modes, a link or interface between the UFS memory system and the host device may also be powered down. The UFS memory system may enter the deep power-down modes based on a command received from the host device or a hardware reset assertion, and exit the deep power-down modes based on a hardware reset de-assertion or power cycling. While in deep power-down modes, the power consumption of the UFS memory device is substantially lower than the power consumption of the UFS memory device in conventional power modes.
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公开(公告)号：US20180107384A1
公开(公告)日：2018-04-19
申请号：US15292675
申请日：2016-10-13
Applicant: QUALCOMM Incorporated
Inventor： Hyunsuk SHIN , David TEB , Hung VUONG
IPC: G06F3/06
CPC classification number: G06F3/061 , G06F3/0607 , G06F3/0635 , G06F3/0679 , G06F13/4022
Abstract: Systems and method are directed to a Universal Flash Storage (UFS) host capable of interfacing one or more UFS devices. The UFS host includes a plurality of mobile-physical-layers (M-PHYs) for supporting one or more lanes of traffic between the UFS host and the one or more UFS devices. A Reference M-PHY MODULE Interface (RMMI) router is coupled between a Unified Protocol link layer (Unipro) and the plurality of M-PHYs. The RMMI router is configurable in a transparent mode to pass traffic, without routing, between the UFS host and a 2-lane embedded UFS device through the two M-PHYs. The RMMI router is configurable in a routing mode, to route traffic to a first M-PHY interfacing a 1-lane embedded UFS device or to a second M-PHY interfacing a 1-lane removable UFS card. The RMMI router is configurable based on metal strap or read only memory (ROM) setting.
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公开(公告)号：US20250103499A1
公开(公告)日：2025-03-27
申请号：US18472642
申请日：2023-09-22
Applicant: QUALCOMM Incorporated
Inventor： Santhosh Reddy AKAVARAM , Chintalapati BHARATH SAI VARMA , Prakhar SRIVASTAVA , Hung VUONG , Ravi Kumar SEPURI
IPC: G06F12/084 , G06F12/02
Abstract: A host device includes a host controller interface (HCI) configured to be coupled to a flash memory device and configured to receive a notification from the flash memory device that a performance threshold register value has been exceeded while the flash memory device is configured to use a shared write buffer. The HCI is also configured to, in response to receiving the notification, perform a remedial action that includes reassigning a portion of a first logical unit (LU).
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公开(公告)号：US20240411481A1
公开(公告)日：2024-12-12
申请号：US18530074
申请日：2023-12-05
Applicant: QUALCOMM Incorporated
Inventor： Chintalapati BHARATH SAI VARMA , Santhosh Reddy AKAVARAM , Sai Naresh GAJAPAKA , Hung VUONG , Radhakrishna MUGADA , Prakhar SRIVASTAVA , Vamsi Krishna SAMBANGI
IPC: G06F3/06
Abstract: Methods that may be performed by a universal flash storage (UFS) system of a computing device for optimizing usage of a shared write booster buffer to extend lifetime. The method may include writing data to a flash storage device including a plurality of logical units of memory by receiving a command identifying a logical unit among the plurality of logical units to store data and data for storage in the identified logical unit, obtaining information indicating a memory write type for the identified logical unit, and writing the received data to either a shared write booster buffer before writing to the identified logical unit of device storage or directly to the identified logical unit of device storage based on the obtained memory write type
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