公开(公告)号：US20240111700A1

公开(公告)日：2024-04-04

申请号：US17960050

申请日：2022-10-04

Applicant: QUALCOMM Incorporated

Inventor： Prakhar SRIVASTAVA ,  Santhosh Reddy AKAVARAM ,  Ravindranath DODDI ,  Ravi Kumar SEPURI

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4031 ,  G06F13/4221 ,  G06F2213/0026

Abstract: Aspects relate to link speed for a peripheral component interconnect. In one aspect, an apparatus includes an interface circuit configured to provide an interface with a multiple lane data link, the data link having a first set of lanes in an active state and a second set of lanes in an idle state and a controller. The controller is configured to receive a request at the controller to change a data rate of the data link to a requested data rate, change the second set of lanes from an idle state to an active state, train the second set of lanes to the requested data rate, transfer data traffic from the first set of lanes to the second set of lanes after the training, and transmit the data traffic on the second set of lanes.

公开(公告)号：US20250076075A1

公开(公告)日：2025-03-06

申请号：US18461419

申请日：2023-09-05

Applicant: QUALCOMM Incorporated

Inventor： Vinod Kumar ENAPAKURTHI ,  Ravi Kumar SEPURI

IPC: G01C21/00

Abstract: Aspects presented herein may enable a UE (e.g., a vehicle, an on-board unit (OBU) of the vehicle, an advanced driver assistance systems (ADAS) of the vehicle, a device running a navigation application, etc.) to download map data in packets based on a set of priorities to improve the efficiency of updating/retrieving map data. In one aspect, a UE calculates a route to a destination based on a current location of the UE and map data. The UE receives, from a server, an indication of updated map data associated with the calculated route, where the updated map data includes a plurality of packets. The UE sets a priority for a download of one or more packets of the plurality of packets based on a set of live parameters. The UE downloads the one or more packets of the updated map data based on the set priority.

公开(公告)号：US20250103499A1

公开(公告)日：2025-03-27

申请号：US18472642

申请日：2023-09-22

Applicant: QUALCOMM Incorporated

Inventor： Santhosh Reddy AKAVARAM ,  Chintalapati BHARATH SAI VARMA ,  Prakhar SRIVASTAVA ,  Hung VUONG ,  Ravi Kumar SEPURI

IPC: G06F12/084 ,  G06F12/02

Abstract: A host device includes a host controller interface (HCI) configured to be coupled to a flash memory device and configured to receive a notification from the flash memory device that a performance threshold register value has been exceeded while the flash memory device is configured to use a shared write buffer. The HCI is also configured to, in response to receiving the notification, perform a remedial action that includes reassigning a portion of a first logical unit (LU).

公开(公告)号：US20250086132A1

公开(公告)日：2025-03-13

申请号：US18463852

申请日：2023-09-08

Applicant: QUALCOMM Incorporated

Inventor： Prakhar SRIVASTAVA ,  Santhosh Reddy AKAVARAM ,  Aditya Singh PATEL ,  Ravi Kumar SEPURI

IPC: G06F13/40

Abstract: The disclosed techniques store certain information of functional modules and lanes to optimize a die-to-die interconnect link. Based on the information, the apparatus can optimize a link width and a multi-module link configuration of the interconnect link. An integrated circuit device includes a first die, a second die, and a die-to-die (D2D) interconnect link connected between the first die and the second die. The D2D interconnect link includes a plurality of lanes grouped into a plurality of modules. The apparatus maintains a training result of the D2D interconnect link based on the training of the D2D interconnect link, the training result including one or more link configurations of the plurality of modules. The apparatus selects a link configuration of the one or more link configurations to configure the D2D interconnect link including one or more of the plurality of modules.

公开(公告)号：US20240111354A1

公开(公告)日：2024-04-04

申请号：US17959996

申请日：2022-10-04

Applicant: QUALCOMM Incorporated

Inventor： Prakhar SRIVASTAVA ,  Santhosh Reddy AKAVARAM ,  Ravindranath DODDI ,  Ravi Kumar SEPURI

IPC: G06F1/3234 ,  G06F13/42

CPC classification number: G06F1/3278 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A new peripheral component interconnect express (PCIe) link state can enhance power saving capabilities of a PCIe link operating in a flow control unit (FLIT) mode. A device can operate a data link with a host in a FLIT mode using fixed-sized packets, the data link being in a partial width link state (PLS) in which a first set of lanes of the data link are in an electrical idle state and a second set of lanes of the data link are in an active state available for data traffic with the host. The device can transition one or more lines of the second set of lanes from the PLS to a partial width standby link state (PSLS) in which the one or more lines of the second set of lanes are in a standby state that has lower power consumption than the active state.