公开(公告)号：US20240354141A1

公开(公告)日：2024-10-24

申请号：US18303101

申请日：2023-04-19

Applicant: QUALCOMM INCORPORATED

Inventor： Prakhar SRIVASTAVA ,  Santhosh Reddy AKAVARAM ,  Ravindranath DODDI ,  Radhakrishna MUGADA

IPC: G06F9/455 ,  G06F13/42

CPC classification number: G06F9/45558 ,  G06F13/4221 ,  G06F2009/45579 ,  G06F2009/45595

Abstract: A multi-lane data communication link, such as a PCIe link, may be configured as virtual links. Each virtual link may correspond to a unique subset of the lanes. Data packets provided by multiple virtual machines and associated virtual functions may be buffered in transmit queues. Each transmit queue may correspond to a unique one of the virtual links. The data may be provided from each of the transmit queues to data transmitting circuitry coupled to active lanes.

公开(公告)号：US20250130898A1

公开(公告)日：2025-04-24

申请号：US18490478

申请日：2023-10-19

Applicant: QUALCOMM Incorporated

Inventor： Subham PANDA ,  Nileshkumar CHANDRAKANTBHAI MOTAWALA ,  Radhakrishna MUGADA ,  Sri Ananda Sai JANNABHATLA ,  Muzaffaruddin MOHAMMED ,  Jyothi RAMIDI ,  Venkatesh PETNIKOTA

IPC: G06F11/10

Abstract: Methods and apparatuses directed to improving performance and data integrity within die architectures. In some examples, a die package includes a memory device, and a processor coupled to the memory device. The memory device may serve as a cache for another memory device. The processor receives a signal indicating that a number of errors have been detected. In response to the signal, the processor reads an error count corresponding to each of multiple memory rows of the memory device. Further, the processor determines a first memory row of the memory rows based on the error counts. The processor also determines a second memory row of the memory rows based on access data characterizing memory accesses of the plurality of rows. The processor further writes data stored at the first memory row to the second memory row of the memory device, and disables the first memory row.

公开(公告)号：US20240411481A1

公开(公告)日：2024-12-12

申请号：US18530074

申请日：2023-12-05

Applicant: QUALCOMM Incorporated

Inventor： Chintalapati BHARATH SAI VARMA ,  Santhosh Reddy AKAVARAM ,  Sai Naresh GAJAPAKA ,  Hung VUONG ,  Radhakrishna MUGADA ,  Prakhar SRIVASTAVA ,  Vamsi Krishna SAMBANGI

IPC: G06F3/06

Abstract: Methods that may be performed by a universal flash storage (UFS) system of a computing device for optimizing usage of a shared write booster buffer to extend lifetime. The method may include writing data to a flash storage device including a plurality of logical units of memory by receiving a command identifying a logical unit among the plurality of logical units to store data and data for storage in the identified logical unit, obtaining information indicating a memory write type for the identified logical unit, and writing the received data to either a shared write booster buffer before writing to the identified logical unit of device storage or directly to the identified logical unit of device storage based on the obtained memory write type