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    EXPANDED DATA LINK WIDTH FOR MAIN BAND CHIP MODULE CONNECTION IN ALTERNATE MODES
    2.
    发明申请
    EXPANDED DATA LINK WIDTH FOR MAIN BAND CHIP MODULE CONNECTION IN ALTERNATE MODES 有权

    公开(公告)号：US20250021504A1

    公开(公告)日：2025-01-16

    申请号：US18352600

    申请日：2023-07-14

    Applicant: QUALCOMM Incorporated

    Inventor： Ravindranath DODDI ,  Umamaheshwaran V ,  Afreen HAIDER ,  Lekhya Pavani GODAVARTHI ,  Harinatha Reddy RAMIREDDY

    IPC: G06F13/40 ,  G06F13/42

    Abstract: Aspects relate to an expanded data link width for a chip connection. In one example a sideband transmitter of a module of a first die is configured to send an expanded data link width enable request to a module partner through a sideband of a die-to-die connection to set an expanded data link width of a main band of the die-to-die connection. The expanded data link width includes data lines of the main band and redundant data lines of the main band reconfigured as data lines. A sideband receiver of the module is configured to receive an expanded data link width enable response from the module partner through the sideband to set the expanded data link width of the main band. A main band transmitter is configured to communicate data with the module partner through the main band using the expanded data link width.

    SYSTEMS AND METHODS FOR REDUCING LATENCY AND IMPROVING PERFORMANCE IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) SYSTEM
    3.
    发明申请
    SYSTEMS AND METHODS FOR REDUCING LATENCY AND IMPROVING PERFORMANCE IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) SYSTEM 有权

    公开(公告)号：US20240427714A1

    公开(公告)日：2024-12-26

    申请号：US18338070

    申请日：2023-06-20

    Applicant: QUALCOMM INCORPORATED

    Inventor： Surendra PARAVADA ,  Madhu Yashwanth BOENAPALLI ,  Vinod Kumar KURUMA ,  Sai Praneeth SREERAM ,  Ravindranath DODDI

    IPC: G06F13/16

    Abstract: A Peripheral Component Interconnect Express (PCIe) system and method achieve reduced latency and improved performance by reconfiguring the PCIe link to use an increased number of lanes for retransmitting data packets held in a replay buffer if one or more data packets transmitted by the TX device are flagged as not acknowledged (NACK) by the RX device. Before retransmitting the NACK-flagged packet(s), the link is reconfigured to use a greater number of lanes, preferably the maximum number of lanes that are available for use, and then the NACK-flagged packet(s) is retransmitted using the greater number of lanes until successful receipt of the NACK-flagged packets has been acknowledged by the RX device. Once the NACK-flagged packet(s) is successfully received by the RX device, the link is reconfigured to use the previous number of lanes and operations of the link resume using the previous number of lanes.

    VARIABLE LINK WIDTH IN TWO DIRECTIONS FOR MAIN BAND CHIP MODULE CONNECTION
    5.
    发明公开
    VARIABLE LINK WIDTH IN TWO DIRECTIONS FOR MAIN BAND CHIP MODULE CONNECTION 审中-公开

    公开(公告)号：US20240354279A1

    公开(公告)日：2024-10-24

    申请号：US18306034

    申请日：2023-04-24

    Applicant: QUALCOMM Incorporated

    Inventor： Ravindranath DODDI ,  Umamaheshwaran V ,  Afreen HAIDER ,  Lekhya Pavani GODAVARTHI ,  Harinatha Reddy RAMIREDDY

    IPC: G06F15/78 ,  G06F13/42

    CPC classification number: G06F15/7825 ,  G06F13/42

    Abstract: Aspects relate to variable link width in two directions for a main band chip module connection. In one aspect, a different set of data lines is active for transmit and receive data lines. In one example a method includes sending an enable request from a module of a first die to a module partner of a second die through a sideband to operate a main band of a die-to-die connection that connects the first die module to the second die module partner at a specified link width, the specified link width having a specified set of data lines of the main band. An enable response is received from the module partner through the sideband to operate the main band at the specified link width and data is communicated with the module partner through the main band using the specified link width in response to receiving the enable response.

    SYSTEMS AND METHODS FOR REDUCING LATENCY AND POWER CONSUMPTION IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) SYSTEM
    8.
    发明申请
    SYSTEMS AND METHODS FOR REDUCING LATENCY AND POWER CONSUMPTION IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) SYSTEM 有权

    公开(公告)号：US20240419613A1

    公开(公告)日：2024-12-19

    申请号：US18337235

    申请日：2023-06-19

    Applicant: QUALCOMM INCORPORATED

    Inventor： Madhu Yashwanth BOENAPALLI ,  Ravindranath DODDI ,  Vinod Kumar KURUMA ,  Surendra PARAVADA ,  Sai Praneeth SREERAM

    IPC: G06F13/16

    Abstract: A Peripheral Component Interconnect Express (PCIe) system and method achieve reduced power consumption and latency. When the link transitions from an active functional state in which the link has a first configuration of N active lanes to a power-saving state, the number of active lanes is collapsed such that M of the N lanes are maintained in an active power-saving state and P of the N lanes are maintained in an electrically idle state, where M, N and P are positive integers and N>P>M. The reduction in lane width reduces power consumption. Bit values specifying the current link configuration can be saved in a control register and read and compared to bit values contained in a link control register before transitioning back to the active functional state. If the bit values match, the active functional state is resumed directly from the recovery state, thereby reducing latency.

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