公开(公告)号：US20250130898A1

公开(公告)日：2025-04-24

申请号：US18490478

申请日：2023-10-19

Applicant: QUALCOMM Incorporated

Inventor： Subham PANDA ,  Nileshkumar CHANDRAKANTBHAI MOTAWALA ,  Radhakrishna MUGADA ,  Sri Ananda Sai JANNABHATLA ,  Muzaffaruddin MOHAMMED ,  Jyothi RAMIDI ,  Venkatesh PETNIKOTA

IPC: G06F11/10

Abstract: Methods and apparatuses directed to improving performance and data integrity within die architectures. In some examples, a die package includes a memory device, and a processor coupled to the memory device. The memory device may serve as a cache for another memory device. The processor receives a signal indicating that a number of errors have been detected. In response to the signal, the processor reads an error count corresponding to each of multiple memory rows of the memory device. Further, the processor determines a first memory row of the memory rows based on the error counts. The processor also determines a second memory row of the memory rows based on access data characterizing memory accesses of the plurality of rows. The processor further writes data stored at the first memory row to the second memory row of the memory device, and disables the first memory row.