公开(公告)号：US20250013572A1

公开(公告)日：2025-01-09

申请号：US18347359

申请日：2023-07-05

Applicant: QUALCOMM Incorporated

Inventor： Sonali JABREVA ,  Sridhar ANUMALA ,  Santhosh Reddy AKAVARAM ,  Prakhar SRIVASTAVA ,  Manish GARG

IPC: G06F12/0855 ,  G06F12/02

Abstract: Aspects relate to interrupting memory access during background operations of a memory device. In one example, a host for a memory device includes background operation circuitry configured to permit a background operation by a memory device. The host is coupled to the memory device through a bus. The host receives an operation completed notification from the memory device to indicate that the memory device has completed performing the background operation. Memory access command circuitry is configured to receive a memory access command. The memory access command concerns reading or writing data to the memory device coupled to the host. The memory access command circuitry initiates a wait at the host for the memory access command, and sends the memory access command to the memory device in response to receiving the operation completed notification.

公开(公告)号：US20240427709A1

公开(公告)日：2024-12-26

申请号：US18338653

申请日：2023-06-21

Applicant: QUALCOMM INCORPORATED

Inventor： Santhosh Reddy AKAVARAM ,  Prakhar SRIVASTAVA ,  Sridhar ANUMALA ,  Ramacharan SUNDARARAMAN ,  Sonali JABREVA ,  Khushboo KUMARI ,  Sanjay VERDU

IPC: G06F13/16

Abstract: Methods and apparatuses are provided to reduce latencies associated with state transitions in die-to-die interconnect architectures. In one example, a physical layer of a die detects a first event indicating a transition to a lower power state. In response to the first event, the physical layer transitions to a lower power state where one or more clock configuration values are read from registers and stored in memory. The physical layer then detects a second event indicating a transition to an active state. In response to the second event, the physical layer reads the clock configuration values from the memory, and writes the clock configuration values to the registers. The physical layer then transitions to a power stabilization state, and remains in the power stabilization state for an amount of time to allow clocks to stabilize. The physical layer then transitions to a training state.

公开(公告)号：US20240427710A1

公开(公告)日：2024-12-26

申请号：US18339904

申请日：2023-06-22

Applicant: QUALCOMM Incorporated

Inventor： Santhosh Reddy AKAVARAM ,  Prakhar SRIVASTAVA ,  Ravindranath DODDI ,  Rajendra Varma PUSAPATI ,  Sonali JABREVA

IPC: G06F13/16

Abstract: Various embodiments include methods and devices for implementing a Peripheral Component Interconnect Express (PCIe) link configuration by a computing device. Embodiments may include selecting, by a PCIe device, a predetermined PCIe link speed based on a PCIe link configuration mode of a PCIe system of a plurality of PCIe link configuration modes of the PCIe system, and selecting, by the PCIe device, a PCIe link width of one lane for configuring the PCIe link. Embodiments may include selecting a PCIe link speed level lower than a current PCIe link speed in response to a reliability indicator exceeding a reliability threshold for a first PCIe link configuration mode. Embodiments may include selecting a maximum PCIe link speed for the PCIe link for a second PCIe link configuration mode. Embodiments may include increasing the PCIe link width in response to a requested bandwidth exceeding a configuration bandwidth of the PCIe link.

公开(公告)号：US20240402923A1

公开(公告)日：2024-12-05

申请号：US18327691

申请日：2023-06-01

Applicant: QUALCOMM Incorporated

Inventor： Santhosh Reddy AKAVARAM ,  Prakhar SRIVASTAVA ,  Sridhar ANUMALA ,  Hung VUONG ,  Sonali JABREVA ,  Khushboo KUMARI

IPC: G06F3/06

Abstract: Aspects of the present disclosure are directed to techniques and procedures for storing data in a data storage device that uses nonvolatile memory (NVM) to store data. The NVM can be organized into logical units that are assigned respective logical unit numbers. The data storage device can report to a host the amount of spare blocks needed for one or more logical units (LUs), and then the host can relinquish some memory blocks to be reallocated as spare blocks. The data storage device can implement a spare block resource management policy per LU and allocate a predetermined amount of spare blocks per LU. The data storage device can implement a spare block resource management policy per memory type and allocate a predetermined amount of spare blocks for LUs with the same memory type.

公开(公告)号：US20240319913A1

公开(公告)日：2024-09-26

申请号：US18189141

申请日：2023-03-23

Applicant: QUALCOMM Incorporated

Inventor： Santhosh Reddy AKAVARAM ,  Sonali JABREVA ,  Prakhar SRIVASTAVA ,  Surendra PARAVADA ,  Yogananda Rao CHILLARIGA ,  Madhu Yashwanth BOENAPALLI

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0604

Abstract: Aspects of the present disclosure provide various techniques, apparatuses, and methods that can improve the write throughout of a data storage device. In some aspects, the storage device can be provided with multiple write buffers to improve write throughput. In some aspects, the data storage device can continue to handle commands using a command queue while performing a write buffer flush operation. Therefore, the data storage device can avoid suspending the write buffer flush operation when a new command is received by the command queue. In some aspects, the storage device can perform a write buffer flush operation when a command queue is not empty.