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公开(公告)号：US09733957B2
公开(公告)日：2017-08-15
申请号：US14479123
申请日：2014-09-05
Applicant: QUALCOMM Incorporated
Inventor： Philip Michael Clovis , Reza Mohammadpourrad , Zeeshan Shafaq Syed
CPC classification number: G06F9/44505 , G06F1/3296 , G06F13/385 , G06F13/4208 , Y02D10/14 , Y02D10/151
Abstract: Changing operating states of a PHY interface which includes a plurality of blocks, changing operating states of a PHY interface includes: receiving parameters indicating desired feature settings of the plurality of blocks for changing the operating state of the PHY interface; and enabling the desired feature settings in a sequence, the sequence based on dependencies between the feature settings, the dependencies being stored in a dependency table.
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公开(公告)号：US09705620B2
公开(公告)日：2017-07-11
申请号：US14858437
申请日：2015-09-18
Applicant: QUALCOMM Incorporated
Inventor： Philip Michael Clovis , Michael Drop , Isaac Berk
CPC classification number: H04J3/0658 , G06F13/1689 , G06F13/4291 , H04L7/0331
Abstract: A memory controller is provided to increment a source timestamp count responsive to a clock signal. Further, the memory controller associates the source timestamp count to a respective word for each endpoint in a plurality of endpoints. The memory controller transmits the received clock signal, a respective data word, and an associated source count to each endpoint. Each endpoint increments a destination count responsive to the clock signal. Each endpoint further transmits its respective word to an external memory responsive to the destination count being greater than or equal to the associated source count by a threshold margin.
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公开(公告)号：US20150364170A1
公开(公告)日：2015-12-17
申请号：US14302727
申请日：2014-06-12
Applicant: QUALCOMM Incorporated
Inventor： Philip Michael Clovis , Yi-Hung Tseng , Xuhao Huang , Sushma Chilukuri
CPC classification number: G11C7/222 , G06F13/1689 , G06F13/4243 , G06F13/4291 , G11C7/10 , G11C7/1066 , G11C7/1093 , G11C29/022 , G11C29/023 , G11C29/028 , H03L7/07 , H03L7/0814
Abstract: A memory controller is provided that drives data and a corresponding first data strobe to a plurality of endpoints. Each endpoint is configured to register the received data from the memory controller responsive to the first data strobe and then to re-register the received data responsive to a second data strobe. A clock synchronization circuit functions to keep the received first data strobe at one of the endpoints sufficiently synchronous with the second data strobe.
Abstract translation: 提供了一种存储器控制器，其将数据和相应的第一数据选通信号驱动到多个端点。 每个端点被配置为响应于第一数据选通从存储器控制器注册接收到的数据，然后响应于第二数据选通来重新注册接收到的数据。 时钟同步电路用于将所接收的第一数据选通信号保持在其中一个端点与第二数据选通脉冲充分同步。
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公开(公告)号：US20140266357A1
公开(公告)日：2014-09-18
申请号：US13831201
申请日：2013-03-14
Applicant: QUALCOMM INCORPORATED
Inventor： Vaishnav Srinivas , Jan Diffenderfer , Philip Michael Clovis , David Ian West
IPC: H03K5/159
CPC classification number: H03K5/159
Abstract: A master measure circuit is disclosed that may select from various nodes on a delay path carrying a signal. The master measure circuit measures the delay for propagation of the signal from one selected node to another selected node and controls an adjustable delay circuit in the delay path accordingly.
Abstract translation: 公开了可以在承载信号的延迟路径上的各个节点进行选择的主测量电路。 主测量电路测量信号从一个选定节点传播到另一个选定节点的延迟，并相应地控制延迟路径中的可调节延迟电路。
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公开(公告)号：US09478268B2
公开(公告)日：2016-10-25
申请号：US14302727
申请日：2014-06-12
Applicant: QUALCOMM Incorporated
Inventor： Philip Michael Clovis , Yi-Hung Tseng , Xuhao Huang , Sushma Chilukuri
CPC classification number: G11C7/222 , G06F13/1689 , G06F13/4243 , G06F13/4291 , G11C7/10 , G11C7/1066 , G11C7/1093 , G11C29/022 , G11C29/023 , G11C29/028 , H03L7/07 , H03L7/0814
Abstract: A memory controller is provided that drives data and a corresponding first data strobe to a plurality of endpoints. Each endpoint is configured to register the received data from the memory controller responsive to the first data strobe and then to re-register the received data responsive to a second data strobe. A clock synchronization circuit functions to keep the received first data strobe at one of the endpoints sufficiently synchronous with the second data strobe.
Abstract translation: 提供了一种存储器控制器，其将数据和相应的第一数据选通信号驱动到多个端点。 每个端点被配置为响应于第一数据选通从存储器控制器注册接收到的数据，然后响应于第二数据选通来重新注册接收到的数据。 时钟同步电路用于将所接收的第一数据选通信号保持在其中一个端点与第二数据选通脉冲充分同步。
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Patent Agency Ranking
公开(公告)号：US20160070582A1
公开(公告)日：2016-03-10
申请号：US14479123
申请日：2014-09-05
Applicant: QUALCOMM Incorporated
Inventor： Philip Michael Clovis , Reza Mohammadpourrad , Zeeshan Shafaq Syed
CPC classification number: G06F9/44505 , G06F1/3296 , G06F13/385 , G06F13/4208 , Y02D10/14 , Y02D10/151
Abstract: Changing operating states of a PHY interface which includes a plurality of blocks, changing operating states of a PHY interface includes: receiving parameters indicating desired feature settings of the plurality of blocks for changing the operating state of the PHY interface; and enabling the desired feature settings in a sequence, the sequence based on dependencies between the feature settings, the dependencies being stored in a dependency table.
Abstract translation: 改变包括多个块的PHY接口的操作状态，改变PHY接口的操作状态包括：接收指示用于改变PHY接口的操作状态的多个块的期望特征设置的参数; 以及在序列中启用期望的特征设置，该序列基于特征设置之间的依赖性，依赖性被存储在依赖关系表中。
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公开(公告)号：US09191193B1
公开(公告)日：2015-11-17
申请号：US14335185
申请日：2014-07-18
Applicant: QUALCOMM Incorporated
Inventor： Xuhao Huang , Yi-Hung Tseng , Philip Michael Clovis , Sushma Chilukuri
CPC classification number: H03L7/10 , H03L7/0812 , H03L7/0814
Abstract: A clock synchronization circuit includes a multi-phase clock generator to generate a plurality of delayed clocks, each delayed clock having a unique delay with regard to a source clock. The clock synchronization circuit further includes a selection circuit that selects one of the delayed clocks according to a phase error to form a local clock driven into a local clock path and received at the clock synchronization circuit as a received local clock. The selection circuit determines the phase error by comparing the received local clock to a reference clock.
Abstract translation: 时钟同步电路包括产生多个延迟时钟的多相时钟发生器，每个延迟时钟具有关于源时钟的唯一延迟。 时钟同步电路还包括选择电路，其根据相位误差选择延迟时钟之一，以形成被驱动到本地时钟路径中并在时钟同步电路处接收的本地时钟作为接收到的本地时钟。 选择电路通过将接收到的本地时钟与参考时钟进行比较来确定相位误差。
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公开(公告)号：US09032358B2
公开(公告)日：2015-05-12
申请号：US13787647
申请日：2013-03-06
Applicant: QUALCOMM Incorporated
Inventor： Vaishnav Srinivas , Robert Won Chol Kim , Philip Michael Clovis , David Ian West
CPC classification number: H01L27/0207 , G06F17/5072 , G06F2217/40
Abstract: An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block.
Abstract translation: 集成电路包括核心逻辑和围绕核心逻辑的外围设置的多个接口块。 多个输入或输出（I / O）电路被分配给多个接口块中的一个。 I / O电路包括耦合到集成电路以外的器件的外部I / O电路和耦合到集成电路的内部I / O电路。 每个接口块包括设置在接口块的第一侧上的第一多个I / O电路和设置在接口块的第二侧上的第二多个I / O电路。 每个接口块还包括用于在第一多个I / O电路和第二多个I / O电路之间的接口块的接口逻辑，以及逻辑集线器，其包括驱动启动逻辑和捕获逻辑的最小长度的时钟分配 形成接口块的I / O电路。
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公开(公告)号：US08957714B2
公开(公告)日：2015-02-17
申请号：US13831201
申请日：2013-03-14
Applicant: QUALCOMM Incorporated
CPC classification number: H03K5/159
Abstract: A master measure circuit is disclosed that may select from various nodes on a delay path carrying a signal. The master measure circuit measures the delay for propagation of the signal from one selected node to another selected node and controls an adjustable delay circuit in the delay path accordingly.
Abstract translation: 公开了可以在承载信号的延迟路径上的各个节点进行选择的主测量电路。 主测量电路测量信号从一个选定节点传播到另一个选定节点的延迟，并相应地控制延迟路径中的可调节延迟电路。
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公开(公告)号：US20140253228A1
公开(公告)日：2014-09-11
申请号：US13787647
申请日：2013-03-06
Applicant: QUALCOMM INCORPORATED
Inventor： Vaishnav Srinivas , Robert Won Chol Kim , Philip Michael Clovis , David Ian West
IPC: H01L27/02
CPC classification number: H01L27/0207 , G06F17/5072 , G06F2217/40
Abstract: An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block.
Abstract translation: 集成电路包括核心逻辑和围绕核心逻辑的外围设置的多个接口块。 多个输入或输出（I / O）电路被分配给多个接口块中的一个。 I / O电路包括耦合到集成电路以外的器件的外部I / O电路和耦合到集成电路的内部I / O电路。 每个接口块包括设置在接口块的第一侧上的第一多个I / O电路和设置在接口块的第二侧上的第二多个I / O电路。 每个接口块还包括用于在第一多个I / O电路和第二多个I / O电路之间的接口块的接口逻辑，以及逻辑集线器，其包括驱动启动逻辑和捕获逻辑的最小长度的时钟分配 形成接口块的I / O电路。
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