On-chip clock generator calibration

    公开(公告)号:US10705557B2

    公开(公告)日:2020-07-07

    申请号:US15942191

    申请日:2018-03-30

    Abstract: Systems, methods, and apparatus for internal on-chip clock calibration for devices coupled to a serial bus are described. A data line of the bus is monitored at a device in order to detect select command signals on the data line, where the select command signals have an accompanying clock signal, such as a burst clock, on a clock line of the serial bus sent concurrently with the command signal. The internal on-chip clock generator in the receiving device utilizes the clock signal occurring with the command signal for calibration, where the select signals are those signals sufficiently long enough for a receiving device to effectively utilize the concurrent clock signal for calibration purposes. In this manner, clock calibration for an internal clock is maintained accurately without the need for an extra clock calibration input.

    FREQUENCY AND POWER MANAGEMENT
    3.
    发明申请
    FREQUENCY AND POWER MANAGEMENT 有权
    频率和电源管理

    公开(公告)号:US20160070582A1

    公开(公告)日:2016-03-10

    申请号:US14479123

    申请日:2014-09-05

    Abstract: Changing operating states of a PHY interface which includes a plurality of blocks, changing operating states of a PHY interface includes: receiving parameters indicating desired feature settings of the plurality of blocks for changing the operating state of the PHY interface; and enabling the desired feature settings in a sequence, the sequence based on dependencies between the feature settings, the dependencies being stored in a dependency table.

    Abstract translation: 改变包括多个块的PHY接口的操作状态,改变PHY接口的操作状态包括:接收指示用于改变PHY接口的操作状态的多个块的期望特征设置的参数; 以及在序列中启用期望的特征设置,该序列基于特征设置之间的依赖性,依赖性被存储在依赖关系表中。

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