公开(公告)号：US11120863B2

公开(公告)日：2021-09-14

申请号：US16752442

申请日：2020-01-24

Applicant: QUALCOMM INCORPORATED

Inventor： Farrukh Aquil ,  Vaishnav Srinivas ,  Mahalingam Nagarajan ,  Yong Xu

IPC: G11C11/4076 ,  G11C7/10 ,  G11C11/409 ,  G06F13/42

Abstract: Signal timing drift in a synchronous dynamic random access memory (SDRAM) system may be compensated for by performing write signal timing training using a multi-purpose command (MPC) first-in-first-out (FIFO) write and MPC FIFO read at periodic intervals interspersed with mission-mode SDRAM traffic. The test result samples obtained from the write signal timing training may be analyzed independently of mission-mode SDRAM traffic. The mission-mode timing of the SDRAM data bit signals relative to the SDRAM write clock signal may be adjusted based on the analysis.

公开(公告)号：US12100474B2

公开(公告)日：2024-09-24

申请号：US17954852

申请日：2022-09-28

Applicant: QUALCOMM Incorporated

Inventor： Yong Xu ,  Satish Krishnamoorthy ,  Boris Dimitrov Andreev ,  Patrick Isakanian ,  Farrukh Aquil ,  Vikas Mahendiyan ,  Ravindra Arvind Khedkar

IPC: G11C7/10 ,  G11C7/14 ,  G11C7/22

CPC classification number: G11C7/222 ,  G11C7/1066 ,  G11C7/14

Abstract: A memory interface circuit has a first differential receiver having a first input coupled to a first reference voltage source, a second differential receiver configured to receive a differential data strobe signal in a pair of complementary signals, a third differential receiver having a first input coupled to a second reference voltage source and a second input configured to receive one of the pair of complementary signals, a clock generation circuit configured to generate a read clock signal based on an output of the second differential receiver and using a qualifying signal output by the third differential receiver to qualify one or more edges in the read clock signal and a data capture circuit clocked by the read clock signal and configured to capture data from the output of the first differential receiver using the one or more edges in the read clock signal.

公开(公告)号：US09734890B1

公开(公告)日：2017-08-15

申请号：US15142306

申请日：2016-04-29

Applicant: QUALCOMM INCORPORATED

Inventor： Farrukh Aquil ,  Michael Drop ,  Vaishnav Srinivas ,  Philip Clovis

IPC: G11C11/409 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G06F13/1678 ,  G06F13/1694 ,  G06F13/4282 ,  G11C7/1072 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4096

Abstract: Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received MRW is either ignored or implemented by the first DRAM.

公开(公告)号：US09734878B1

公开(公告)日：2017-08-15

申请号：US15142316

申请日：2016-04-29

Applicant: QUALCOMM INCORPORATED

Inventor： Farrukh Aquil ,  Michael Drop ,  Vaishnav Srinivas ,  Philip Clovis

IPC: G11C7/10 ,  G11C11/408 ,  G11C11/407 ,  G11C11/4076 ,  G06F13/42 ,  G06F13/16

CPC classification number: G11C11/4093 ,  G06F13/1678 ,  G06F13/1694 ,  G06F13/4282 ,  G11C7/1072 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4096

Abstract: Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received MRW is either ignored or implemented by the first DRAM.

公开(公告)号：US11493949B2

公开(公告)日：2022-11-08

申请号：US16832855

申请日：2020-03-27

Applicant: Qualcomm Incorporated

Inventor： Farrukh Aquil ,  Mahalingam Nagarajan ,  Vaishnav Srinivas ,  Yong Xu

IPC: G06F1/12 ,  G06F1/08 ,  G06F13/16

Abstract: Methods and apparatuses for improve clocking scheme to reduce power consumption are presented. The apparatus includes a host configured to communicate with a memory via a link. The host is further configured to receive a first clock from the memory; to receive, based on the first clock, data from the memory, in a first mode of a read operation; to generate a second clock, the second clock being generated independent of the first clock; and to receive, based on the second clock, data from the memory, in a second mode of the read operation.