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    Schottky device
    1.
    发明授权
    Schottky device 有权
    肖特基装置

    公开(公告)号：US08338906B2

    公开(公告)日：2012-12-25

    申请号：US12329677

    申请日：2008-12-08

    Applicant: Ping-Chun Yeh ,  Der-Chyang Yeh ,  Ruey-Hsin Liu ,  Mingo Liu

    Inventor： Ping-Chun Yeh ,  Der-Chyang Yeh ,  Ruey-Hsin Liu ,  Mingo Liu

    IPC: H01L29/66

    CPC classification number: H01L27/0814 ,  H01L29/0692 ,  H01L29/417 ,  H01L29/872

    Abstract: An integrated circuit structure has a metal silicide layer formed on an n-type well region, a p-type guard ring formed on the n-type well region and encircling the metal silicide layer. The outer portion of the metal silicide layer extends to overlap the inner edge of the guard ring, and a Schottky barrier is formed at the junction of the internal portion of the metal silicide layer and the well region. A conductive contact is in contact with the internal portion and the outer portion of the metal silicide layer.

    Abstract translation: 集成电路结构具有形成在n型阱区上的金属硅化物层，形成在n型阱区上并环绕金属硅化物层的p型保护环。 金属硅化物层的外部部分延伸成与保护环的内边缘重叠，并且在金属硅化物层的内部部分与阱区域的接合处形成肖特基势垒。 导电接触件与金属硅化物层的内部部分和外部部分接触。

    SCHOTTKY DEVICE
    2.
    发明申请
    SCHOTTKY DEVICE 有权
    肖特设备

    公开(公告)号：US20090283841A1

    公开(公告)日：2009-11-19

    申请号：US12329677

    申请日：2008-12-08

    Applicant: Ping-Chun Yeh ,  Der-Chyang Yeh ,  Ruey-Hsin Liu ,  Mingo Liu

    Inventor： Ping-Chun Yeh ,  Der-Chyang Yeh ,  Ruey-Hsin Liu ,  Mingo Liu

    IPC: H01L29/872 ,  H01L29/78 ,  H01L27/088

    CPC classification number: H01L27/0814 ,  H01L29/0692 ,  H01L29/417 ,  H01L29/872

    Abstract: An integrated circuit structure has a metal silicide layer formed on an n-type well region, a p-type guard ring formed on the n-type well region and encircling the metal silicide layer. The outer portion of the metal silicide layer extends to overlap the inner edge of the guard ring, and a Schottky barrier is formed at the junction of the internal portion of the metal silicide layer and the well region. A conductive contact is in contact with the internal portion and the outer portion of the metal silicide layer.

    Abstract translation: 集成电路结构具有形成在n型阱区上的金属硅化物层，形成在n型阱区上并环绕金属硅化物层的p型保护环。 金属硅化物层的外部部分延伸成与保护环的内边缘重叠，并且在金属硅化物层的内部部分与阱区域的接合处形成肖特基势垒。 导电接触件与金属硅化物层的内部部分和外部部分接触。

    Lateral DMOS device with dummy gate
    4.
    发明授权
    Lateral DMOS device with dummy gate 有权
    具有虚拟门的侧面DMOS设备

    公开(公告)号：US09450056B2

    公开(公告)日：2016-09-20

    申请号：US13351295

    申请日：2012-01-17

    Applicant: Chun-Wai Ng ,  Ruey-Hsin Liu ,  Jun Cai ,  Hsueh-Liang Chou ,  Chi-Chih Chen

    Inventor： Chun-Wai Ng ,  Ruey-Hsin Liu ,  Jun Cai ,  Hsueh-Liang Chou ,  Chi-Chih Chen

    IPC: H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06

    CPC classification number: H01L29/7816 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368

    Abstract: An LDMOS transistor with a dummy gate comprises an extended drift region formed over a substrate, a drain region formed in the extended drift region, a channel region formed in the extended drift region, a source region formed in the channel region and a dielectric layer formed over the extended drift region. The LDMOS transistor with a dummy gate further comprises an active gate formed over the channel region and a dummy gate formed over the extended drift region. The dummy gate helps to reduce the gate charge of the LDMOS transistor while maintaining the breakdown voltage of the LDMOS transistor.

    Abstract translation: 具有伪栅极的LDMOS晶体管包括形成在衬底上的扩展漂移区，形成在扩展漂移区中的漏极区，形成在扩展漂移区中的沟道区，形成在沟道区中的源极区和形成的电介质层 在扩展漂移区域上。 具有伪栅极的LDMOS晶体管还包括形成在沟道区上的有源栅极和形成在扩展漂移区上的伪栅极。 虚拟栅极有助于降低LDMOS晶体管的栅极电荷，同时保持LDMOS晶体管的击穿电压。

    Metal/polysilicon gate trench power mosfet
    6.
    发明授权
    Metal/polysilicon gate trench power mosfet 有权
    金属/多晶硅栅沟槽功率MOSFET

    公开(公告)号：US08933507B2

    公开(公告)日：2015-01-13

    申请号：US13545131

    申请日：2012-07-10

    Applicant: Chun-Wai Ng ,  Hsueh-Liang Chou ,  Po-Chih Su ,  Ruey-Hsin Liu

    Inventor： Chun-Wai Ng ,  Hsueh-Liang Chou ,  Po-Chih Su ,  Ruey-Hsin Liu

    IPC: H01L29/66

    CPC classification number: H01L29/7813 ,  H01L21/823418 ,  H01L21/823456 ,  H01L27/0922 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/4941 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7809 ,  H01L29/7816 ,  H01L29/7835

    Abstract: The present disclosure relates to a power MOSFET device having a relatively low resistance hybrid gate electrode that enables good switching performance. In some embodiments, the power MOSFET device has a semiconductor body. An epitaxial layer is disposed on the semiconductor body. A hybrid gate electrode, which controls the flow of electrons between a source electrode and a drain electrode, is located within a trench extending into the epitaxial layer. The hybrid gate electrode has an inner region having a low resistance metal, an outer region having a polysilicon material, and a barrier region disposed between the inner region and the outer region. The low resistance of the inner region provides for a low resistance to the hybrid gate electrode that enables good switching performance for the power MOSFET device.

    Abstract translation: 本公开涉及具有相对低电阻的混合栅电极的功率MOSFET器件，其实现良好的开关性能。 在一些实施例中，功率MOSFET器件具有半导体本体。 外延层设置在半导体本体上。 控制源电极和漏电极之间的电子流的混合栅电极位于延伸到外延层中的沟槽内。 混合栅极具有具有低电阻金属的内部区域，具有多晶硅材料的外部区域和设置在内部区域和外部区域之间的阻挡区域。 内部区域的低电阻提供了对功率MOSFET器件具有良好开关性能的混合栅电极的低电阻。

    Transistor and method of manufacturing the same
    7.
    发明授权
    Transistor and method of manufacturing the same 有权
    晶体管及其制造方法

    公开(公告)号：US08796760B2

    公开(公告)日：2014-08-05

    申请号：US13420248

    申请日：2012-03-14

    Applicant: Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu

    Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/7809 ,  H01L21/265 ,  H01L21/2815 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

    Abstract: A manufacture includes a doped layer, a body structure over the doped layer, a trench defined in the doped layer, an insulator partially filling the trench, and a first conductive feature buried in, and separated from the doped layer and the body structure by, the insulator. The doped layer has a first type doping. The body structure has an upper surface and includes a body region. The body region has a second type doping different from the first type doping. The trench has a bottom surface. The first conductive feature extends from a position substantially leveled with the upper surface of the body structure toward the bottom surface of the trench. The first conductive feature overlaps the doped layer for an overlapping distance, and the overlapping distance ranging from 0 to 2 μm.

    Abstract translation: 一种制造方法包括掺杂层，掺杂层上的体结构，在掺杂层中限定的沟槽，部分地填充沟槽的绝缘体，以及掩埋在掺杂层和体结构中并与掺杂层和体结构分离的第一导电特征， 绝缘体。 掺杂层具有第一类掺杂。 身体结构具有上表面并且包括身体区域。 体区具有不同于第一类掺杂的第二类型掺杂。 沟槽有一个底面。 第一导电特征从基本上与主体结构的上表面平齐的位置延伸到沟槽的底表面。 第一导电特征与掺杂层重叠重叠距离，重叠距离范围为0至2μm。

    Vertical Power MOSFET and Methods for Forming the Same
    9.
    发明申请
    Vertical Power MOSFET and Methods for Forming the Same 有权
    垂直功率MOSFET及其形成方法

    公开(公告)号：US20130320431A1

    公开(公告)日：2013-12-05

    申请号：US13486768

    申请日：2012-06-01

    Applicant: Po-Chih Su ,  Hsueh-Liang Chou ,  Ruey-Hsin Liu ,  Chun-Wai Ng

    Inventor： Po-Chih Su ,  Hsueh-Liang Chou ,  Ruey-Hsin Liu ,  Chun-Wai Ng

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/66666 ,  H01L21/30604 ,  H01L21/743 ,  H01L21/76877 ,  H01L21/823456 ,  H01L21/823487 ,  H01L21/823493 ,  H01L27/088 ,  H01L27/098 ,  H01L29/0847 ,  H01L29/402 ,  H01L29/7827 ,  H01L29/7833

    Abstract: A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate dielectric. A drain region is disposed at a top surface of the semiconductor region and adjacent to the gate electrode. A gate spacer is on a sidewall of the gate electrode. A dielectric layer is disposed over the gate electrode and the gate spacer. A conductive field plate is over the dielectric layer, wherein the conductive field plate has a portion on a drain side of the gate electrode. A deep metal via is disposed in the semiconductor region. A source electrode is underlying the semiconductor region, wherein the source electrode is electrically shorted to the conductive field plate through the deep metal via.

    Abstract translation: 一种器件包括半导体芯片中的半导体区域，半导体区域上的栅极电介质层和栅极电介质上的栅电极。 漏极区域设置在半导体区域的顶表面并与栅电极相邻。 栅极间隔物位于栅电极的侧壁上。 电介质层设置在栅电极和栅间隔物上。 导电场板在电介质层的上方，其中导电场板具有在栅电极的漏极侧的一部分。 深金属通孔设置在半导体区域中。 源电极位于半导体区域的下方，其中源电极通过深金属通孔与导电场板电短路。

    Stacked and tunable power fuse
    10.
    发明授权
    Stacked and tunable power fuse 有权
    堆叠和可调电源保险丝

    公开(公告)号：US08598679B2

    公开(公告)日：2013-12-03

    申请号：US12956025

    申请日：2010-11-30

    Applicant: Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai

    Inventor： Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai

    IPC: H01L23/52

    CPC classification number: H01L27/0288 ,  H01L23/5256 ,  H01L27/0255 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided.

    Abstract translation: 本公开提供了一种半导体器件，其包括晶体管，其包括衬底，源极，漏极和栅极以及堆叠在晶体管上的熔丝。 保险丝包括耦合到晶体管的漏极的阳极触点，阴极触点和分别经由第一肖特基二极管和第二肖特基二极管耦合到阴极触点和阳极触点的电阻器。 还提供了一种制造这种半导体器件的方法。

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