公开(公告)号：US11817323B2

公开(公告)日：2023-11-14

申请号：US17188005

申请日：2021-03-01

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo Okita ,  Atsushi Harikai ,  Akihiro Itou

IPC: H01L21/311 ,  H01L21/78 ,  H01L21/683 ,  H01L21/3065 ,  H01L21/02

CPC classification number: H01L21/31138 ,  H01L21/6836 ,  H01L21/78 ,  H01L21/02274 ,  H01L21/30655 ,  H01L2221/68327

Abstract: An etching method including: a preparation step of preparing a resin layer and an electronic component supported thereby; and a resin etching step of etching the resin layer. The electronic component has a first surface covered with a protective film, a second surface opposite thereto, and a sidewall therebetween. The second surface is facing the resin layer. The resin layer is larger than the electronic component when seen from the first surface side. The resin etching step includes: a deposition step of depositing a first film, using a first plasma, on a surface of the protective film and a surface of the resin layer; and a removal step of removing, using a second plasma, the first film deposited on the resin layer and at least part of the resin layer. The deposition and removal steps are alternately repeated, with the protective film allowed to continue to exist.

公开(公告)号：US11335564B2

公开(公告)日：2022-05-17

申请号：US16993466

申请日：2020-08-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Akihiro Itou ,  Atsushi Harikai ,  Toshiyuki Takasaki ,  Shogo Okita

IPC: H01L21/3065 ,  H01L21/02

Abstract: An element chip smoothing method including: an element chip preparation step of preparing at least one element chip including a first surface covered with a resin film, a second surface opposite the first surface, and a sidewall connecting the first surface to the second surface and having ruggedness; a sidewall cleaning step of exposing the element chip to a first plasma, to remove deposits adhering to the sidewall, with the resin film allowed to continue to exist; a sidewall oxidation step of exposing the element chip to a second plasma, after the sidewall cleaning step, to oxidize a surface of the sidewall, with the resin film allowed to continue to exist; and a sidewall etching step of exposing the element chip to a third plasma, after the sidewall oxidation step, to etch the sidewall, with the resin film allowed to continue to exist.

公开(公告)号：US11830758B2

公开(公告)日：2023-11-28

申请号：US17456908

申请日：2021-11-30

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Shogo Okita ,  Akihiro Itou

IPC: H01L21/3065 ,  H01L21/683 ,  H01J37/32

CPC classification number: H01L21/6836 ,  H01J37/32495 ,  H01J37/32862 ,  H01L21/3065

Abstract: A plasma processing method including: a process of placing a work piece on a stage provided in a chamber, the work piece including a substrate and a holding member having an adhesive layer on a surface and holding the substrate via the adhesive layer, and having an exposed portion where the adhesive layer is exposed outside the substrate; and a plasma etching process of etching the substrate with a plasma generated in the chamber, with the exposed portion exposed to the plasma. In response to occurrence of an interruption in the plasma etching process, a cleaning process of exposing a surface of the substrate to a plasma containing an oxidizing gas is performed, and then the plasma etching process is resumed.

公开(公告)号：US10923362B2

公开(公告)日：2021-02-16

申请号：US16939492

申请日：2020-07-27

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Noriyuki Matsubara ,  Shogo Okita ,  Hidehiko Karasaki

IPC: H01L21/20 ,  H01L21/306 ,  G03F7/038 ,  G03F7/40 ,  H01L21/78 ,  H01L29/06 ,  H01L21/311 ,  H01L21/67 ,  H01L21/3065 ,  H01L21/82 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/308 ,  H01L21/683 ,  H01J37/00 ,  H01L23/00

Abstract: A manufacturing process of an element chip comprises steps of preparing a substrate including a plurality of etching regions and element regions each containing a plurality of convex and concave portions, holding the substrate and a frame with a holding sheet, forming a protective film by applying a first mixture to form a coated film above the substrate and by drying the coated film to form the protective film along the convex and concave portions, the first mixture containing a water-soluble first resin, water and a water-soluble organic solvent and has a vapor pressure higher than water, removing the protective film by irradiating a laser beam thereon to expose the substrate in the etching regions, plasma-etching the substrate along the etching regions while maintaining the protective film in the element regions to individualize the substrate, and removing the protective film by contacting the protective film with an aqueous rinse solution.

公开(公告)号：US10242914B2

公开(公告)日：2019-03-26

申请号：US15952342

申请日：2018-04-13

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo Okita ,  Noriyuki Matsubara ,  Atsushi Harikai ,  Akihiro Itou

IPC: H01L21/027 ,  H01L21/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  G03F7/20 ,  G03F7/32 ,  G03F7/039 ,  G03F7/16 ,  G03F7/09 ,  H01J37/32

Abstract: A semiconductor chip manufacturing method includes forming a mask on a surface of a semiconductor wafer, forming an opening on the mask, exposing a dividing region of the semiconductor wafer, a rear surface of the semiconductor wafer is held by a dicing tape via an adhesive layer, singulating the semiconductor wafer into a plurality of semiconductor chips by etching the semiconductor wafer exposed to the opening with a first plasma until the semiconductor wafer reaches a rear surface, removing the mask so that the plurality of element chips from which the mask is removed are held by the holding sheet via the adhesive layer.At the time of removing the mask, the mask is removed from an alkaline developer having a dissolution rate of the mask larger than a dissolution rate of the adhesive layer.

公开(公告)号：US10177063B2

公开(公告)日：2019-01-08

申请号：US15426181

申请日：2017-02-07

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Bunzi Mizuno ,  Mitsuru Hiroshima ,  Shogo Okita ,  Noriyuki Matsubara ,  Atsushi Harikai

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/268 ,  H01L21/311 ,  H01L21/56 ,  H01L21/78 ,  H01L23/544 ,  H01L21/683 ,  H01L21/02 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/67

Abstract: A method for manufacturing an element chip includes a protection film stacking step of staking a protection film to the element region, and the dividing region, the part of the exposed second damaged region and a protection film etching step of removing a part of the protection film which is stacked on the dividing region and the protection film which is stacked on the element region by exposing the substrate to second plasma and remaining the protection film for covering the part of the second damaged region. Furthermore, the method for manufacturing an element chip includes a plasma dicing step of dividing the substrate to a plurality of element chips by exposing the substrate to third plasma in a state where the second main surface is supported by a supporting member.

公开(公告)号：US09799495B2

公开(公告)日：2017-10-24

申请号：US14834992

申请日：2015-08-25

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Shogo Okita ,  Bunji Miizuno ,  Tomohiro Okumura

IPC: H01J37/32 ,  H01L21/67 ,  H01L21/683 ,  H01L21/687

CPC classification number: H01J37/32724 ,  H01J37/321 ,  H01J37/32651 ,  H01J37/32697 ,  H01L21/67092 ,  H01L21/67109 ,  H01L21/6831 ,  H01L21/68728 ,  H01L21/68742

Abstract: A plasma processing apparatus that performs plasma processing on a substrate held on a transport carrier including an annular frame and a holding sheet. The apparatus includes a process chamber; a process gas supply unit that supplies process gas to the process chamber; a decompressing mechanism that decompresses the process chamber; a plasma excitation device that generates plasma in the process chamber; a stage in the chamber, on which the transport carrier is loaded; a cooling mechanism for cooling the stage; a cover that partly covers the holding sheet and the frame and that has a window section through which the substrate is partly exposed to plasma; a correction member that presses the frame onto the stage and corrects warpage of the frame; and a movement device that moves the correction member. The correction member is provided separately from the cover to be covered by the cover.

公开(公告)号：US09698073B2

公开(公告)日：2017-07-04

申请号：US15264921

申请日：2016-09-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Shogo Okita ,  Noriyuki Matsubara ,  Mitsuru Hiroshima ,  Mitsuhiro Okune

IPC: H01L21/318 ,  H01L21/78 ,  H01L21/683 ,  H01L23/31 ,  H01L21/02 ,  H01L23/29

CPC classification number: H01L23/3185 ,  H01L21/0212 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/293 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: In a plasma processing step in a method of manufacturing an element chip in which a plurality of element chips are manufactured by dividing a substrate, which has a plurality of element regions, the substrate is divided into element chips by exposing the substrate to first plasma. In a protection film forming step of forming a protection film covering a side surface and a second surface by exposing the element chips to second plasma of which raw material gas is mixed gas of carbon fluoride and helium, protection film forming conditions are set such that a thickness of a second protection film of the second surface is greater than a thickness of a first protection film of the side surface.

公开(公告)号：US20160293456A1

公开(公告)日：2016-10-06

申请号：US15000789

申请日：2016-01-19

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo Okita ,  Atsushi Harikai ,  Noriyuki Matsubara

IPC: H01L21/677 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/683 ,  H01L21/78

CPC classification number: H01L21/3065 ,  H01J37/32568 ,  H01J37/32697 ,  H01J37/32715 ,  H01J37/32724 ,  H01L21/67109 ,  H01L21/6833 ,  H01L21/6836 ,  H01L21/68742 ,  H01L21/78 ,  H01L2221/68327

Abstract: A plasma processing apparatus includes: a reaction chamber; a plasma generation unit; a stage disposed inside the reaction chamber; an electrostatic chuck mechanism including an electrode portion inside the stage; a heater inside the stage; a support portion which supports a conveyance carrier between a stage-mounted position on the stage and a transfer position distant from the stage upward; and an elevation mechanism which elevates and lowers the support portion relative to the stage. In a case in which the conveyance carrier is mounted on the stage by lowering the support portion, application of voltage to the electrode portion is started in a state that the stage is being heated, and the plasma generation unit generates plasma after at least a part of an outer circumferential portion of a holding sheet holding the conveyance carrier contacts the stage and also after the heating of the stage is stopped.

Abstract translation: 一种等离子体处理装置，包括：反应室; 等离子体发生单元; 设置在反应室内的阶段; 静电吸盘机构，其包括在所述平台内部的电极部分; 舞台内的加热器; 支撑部分，其支撑在舞台上的舞台安装位置和远离舞台的传送位置之间的传送载体; 以及升降机构，其使支撑部相对于台升高并降低。 在通过降低支撑部分将输送载体安装在载台上的情况下，在加热阶段的状态下开始对电极部施加电压，等离子体产生单元在至少一部分之后产生等离子体 保持输送载体的保持片的外周部与台架接触，并且在台架的加热停止之后。

公开(公告)号：US12300482B2

公开(公告)日：2025-05-13

申请号：US17663452

申请日：2022-05-16

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidehiko Karasaki ,  Shogo Okita

IPC: H01L21/02 ,  H01L21/463 ,  H01L21/68 ,  H01L23/544

Abstract: A method including: a step of preparing a substrate that includes a first layer having a first principal surface provided with a dicing region, and a mark, and a second principal surface, and includes a semiconductor layer; a step of covering a first region corresponding to the mark on the second principal surface, with a resist film; a step of forming a metal film on the second principal surface; a step of removing the resist film, to expose the semiconductor layer corresponding to the first region; a step of imaging the substrate, with a camera, to detect a position of the mark through the semiconductor layer, and calculating a second region corresponding to the dicing region on a surface of the metal film; and a step of irradiating a laser beam to the second region, to remove the metal film and expose the semiconductor layer corresponding to the second region.