公开(公告)号：US10923362B2

公开(公告)日：2021-02-16

申请号：US16939492

申请日：2020-07-27

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Noriyuki Matsubara ,  Shogo Okita ,  Hidehiko Karasaki

IPC: H01L21/20 ,  H01L21/306 ,  G03F7/038 ,  G03F7/40 ,  H01L21/78 ,  H01L29/06 ,  H01L21/311 ,  H01L21/67 ,  H01L21/3065 ,  H01L21/82 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/308 ,  H01L21/683 ,  H01J37/00 ,  H01L23/00

Abstract: A manufacturing process of an element chip comprises steps of preparing a substrate including a plurality of etching regions and element regions each containing a plurality of convex and concave portions, holding the substrate and a frame with a holding sheet, forming a protective film by applying a first mixture to form a coated film above the substrate and by drying the coated film to form the protective film along the convex and concave portions, the first mixture containing a water-soluble first resin, water and a water-soluble organic solvent and has a vapor pressure higher than water, removing the protective film by irradiating a laser beam thereon to expose the substrate in the etching regions, plasma-etching the substrate along the etching regions while maintaining the protective film in the element regions to individualize the substrate, and removing the protective film by contacting the protective film with an aqueous rinse solution.

公开(公告)号：US10546783B2

公开(公告)日：2020-01-28

申请号：US16008280

申请日：2018-06-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Noriyuki Matsubara ,  Hidehiko Karasaki

IPC: H01L21/82 ,  H01L21/683 ,  B23K26/364 ,  H01L21/67 ,  H01L21/308 ,  H01L21/3065

Abstract: Provided is a manufacturing process of an element chip, which comprises a preparing step for preparing a substrate containing element regions and dicing regions, a holding step for holding the substrate and a frame with a holding sheet, an applicating step for applying a resin material solution containing a resin constituent and a solvent on the substrate to form a coated layer containing the resin constituent and the solvent thereon, a heating step for heating the substrate held on the holding sheet through a heat shielding member shielding the frame and the holding sheet to substantially remove the solvent from the coated layer, thereby to form a resin layer, a patterning step for patterning the resin layer to expose the substrate in the dicing regions, and a dicing step for dicing the substrate into element chips by plasma-etching the substrate.

公开(公告)号：US11319458B2

公开(公告)日：2022-05-03

申请号：US17280185

申请日：2020-03-09

Applicant: GOO CHEMICAL CO., LTD. ,  Panasonic Intellectual Property Management Co., Ltd.

Inventor： Teru Sakakibara ,  Shinya Komabiki ,  Koji Maeda ,  Hidehiko Karasaki

IPC: H01L21/78 ,  C09D167/02 ,  C08G63/183 ,  C08G63/189 ,  H01L21/683

Abstract: A protective composition contains a water-soluble polyester resin including a polyvalent carboxylic acid residue and a polyvalent alcohol residue. The polyvalent carboxylic acid residue includes: a polyvalent carboxylic acid residue having a metal sulfonate group; and a naphthalene dicarboxylic acid residue. The proportion of the polyvalent carboxylic acid residue to the polyvalent carboxylic acid residue falls within the range from 25 mol % to 70 mol %. The proportion of the naphthalene dicarboxylic acid residue to the polyvalent carboxylic acid residue falls within the range from 30 mol % to 75 mol %.

公开(公告)号：US10410924B2

公开(公告)日：2019-09-10

申请号：US15860827

申请日：2018-01-03

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidehiko Karasaki ,  Hidefumi Saeki ,  Atsushi Harikai

IPC: H01L21/78 ,  H01L23/544 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/02 ,  B23K26/359 ,  H01L21/82 ,  H01L21/67 ,  H01L21/683 ,  B23K26/062 ,  H01J37/32 ,  B23K103/00

Abstract: Provided is a manufacturing process of an element chip, which comprises a preparation step for preparing a substrate including a semiconductor layer having first and second sides and a wiring layer on the first side thereof, the substrate having a plurality of dicing regions and element regions defined by the dicing regions, a scribing step for radiating a laser beam towards the first side of the wiring layer onto the dicing regions to form apertures exposing the semiconductor layer along the dicing regions, and a dicing step for dicing the substrate along the apertures into a plurality of the element chips, wherein the laser beam has a beam profile having a M-shaped distribution whose peripheral intensity is greater than a central intensity in a width direction of the laser beam along the dicing regions.

公开(公告)号：US12300482B2

公开(公告)日：2025-05-13

申请号：US17663452

申请日：2022-05-16

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidehiko Karasaki ,  Shogo Okita

IPC: H01L21/02 ,  H01L21/463 ,  H01L21/68 ,  H01L23/544

Abstract: A method including: a step of preparing a substrate that includes a first layer having a first principal surface provided with a dicing region, and a mark, and a second principal surface, and includes a semiconductor layer; a step of covering a first region corresponding to the mark on the second principal surface, with a resist film; a step of forming a metal film on the second principal surface; a step of removing the resist film, to expose the semiconductor layer corresponding to the first region; a step of imaging the substrate, with a camera, to detect a position of the mark through the semiconductor layer, and calculating a second region corresponding to the dicing region on a surface of the metal film; and a step of irradiating a laser beam to the second region, to remove the metal film and expose the semiconductor layer corresponding to the second region.

公开(公告)号：US11289428B2

公开(公告)日：2022-03-29

申请号：US16872801

申请日：2020-05-12

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Kiyoshi Arita ,  Shogo Okita ,  Hidehiko Karasaki

IPC: H01L21/00 ,  H01L23/544 ,  H01L21/66 ,  H01L21/268 ,  H01L21/78 ,  B23K26/57 ,  B23K26/18 ,  B23K26/351 ,  B23K26/0622 ,  B23K103/00 ,  B23K101/40

Abstract: An element chip manufacturing method including: preparing a semiconductor substrate including a first layer having a first principal surface, and a second layer having a second principal surface, the first layer provided with element regions, a dicing region, and an alignment mark, wherein the first layer includes a semiconductor layer, and the second layer includes a metal layer adjacent to the semiconductor layer; irradiating a first laser beam absorbed in the metal film and passing through the semiconductor layer, from the second principal surface side to a first region corresponding to the mark; imaging the semiconductor substrate from the second principal surface side with a camera, and then calculating a second region corresponding to the dicing region on the second principal surface; irradiating a second laser beam to the second region from the second principal surface side; and dicing the semiconductor substrate into a plurality of element chips.

公开(公告)号：US10607846B2

公开(公告)日：2020-03-31

申请号：US16103025

申请日：2018-08-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidehiko Karasaki ,  Noriyuki Matsubara ,  Atsushi Harikai ,  Hidefumi Saeki

IPC: H01L21/00 ,  H01L21/3065 ,  B23K26/0622 ,  H01L21/02 ,  H01L21/475 ,  H01L21/67 ,  H01L21/683 ,  H01L21/78

Abstract: Method of manufacturing an element chip which can suppress residual debris in plasma dicing. A back surface of a semiconductor wafer is held on a dicing tape. Then, a surface of the wafer is coated with a mask that includes a water-insoluble lower mask and a water-soluble upper mask. Subsequently, an opening is formed in the mask by irradiating the mask with laser light to expose a dividing region. Then, the semiconductor wafer is caused to come into contact with water to remove the upper mask covering each of the element regions while leaving the lower layer. After that, the wafer is exposed to plasma to perform etching on the dividing region exposed from the opening until the etching reaches the back surface, thereby dicing the semiconductor wafer into a plurality of element chips. Thereafter, the lower layer mask left on the front surface of the semiconductor chips is removed.

公开(公告)号：US10147646B2

公开(公告)日：2018-12-04

申请号：US15811733

申请日：2017-11-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidehiko Karasaki ,  Hidefumi Saeki ,  Atsushi Harikai

IPC: H01L21/78 ,  H01L21/268

Abstract: A manufacturing process of an element chip comprises a preparation step for preparing a substrate, the substrate including first and second streets crossing each other to define a plurality of element regions. Also, it comprises a first shallow-groove formation step for radiating a laser beam along the first streets to form a plurality of first shallow grooves being shallower than a thickness of the substrate, a second shallow-groove formation step for radiating the laser beam along the second streets to form a plurality of second shallow grooves being shallower than a thickness of the substrate, a first groove formation step for radiating the laser beam along the first shallow grooves to form a plurality of first grooves, and a plasma dicing step for etching the substrate along the first grooves and the second shallow grooves by a plasma exposure to dice the substrate into a plurality of element chips.

公开(公告)号：US11688641B2

公开(公告)日：2023-06-27

申请号：US16881165

申请日：2020-05-22

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidefumi Saeki ,  Hidehiko Karasaki ,  Shogo Okita ,  Atsushi Harikai ,  Akihiro Itou

IPC: H01L21/82 ,  H01L21/56 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/78

CPC classification number: H01L21/82 ,  H01L21/3065 ,  H01L21/31122 ,  H01L21/31127 ,  H01L21/568

Abstract: An element chip manufacturing method including: attaching a substrate via a die attach film (DAF) to a holding sheet; forming a protective film that covers the substrate; forming an opening in the protective film with a laser beam, to expose the substrate in the dicing region therefrom; exposing the substrate to a first plasma to etch the substrate exposed from the opening, so that a plurality of element chips are formed from the substrate and so that the DAF is exposed from the opening; exposing the substrate to a second plasma to etch the die attach film exposed from the opening, so that the DAF is split so as to correspond to the element chips; and detaching the element chips from the holding sheet, together with the split DAF. The DAF is larger than the substrate. The method includes irradiating the laser beam to the DAF protruding from the substrate.

公开(公告)号：US10896849B2

公开(公告)日：2021-01-19

申请号：US16426116

申请日：2019-05-30

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidehiko Karasaki ,  Shogo Okita ,  Noriyuki Matsubara ,  Hidefumi Saeki

IPC: H01L21/78 ,  B23K26/40 ,  H01L21/3065 ,  B23K26/364 ,  H01L21/308 ,  H01L21/02 ,  B23K101/40

Abstract: A substrate has first and second surfaces, and includes a plurality of element regions and dividing region defining the element regions. A method for manufacturing an element chip includes: a step of spray coating, to the first surface of the substrate, a mixture containing a water-soluble resin and an organic solvent having a higher vapor pressure than water, and drying the coated mixture at a temperature of 50° C. or less, to form a protective film; a laser grooving step of removing portions of the protective film covering the dividing regions; a step of dicing the substrate into element chips by plasma etching the substrate; and a step of removing the portions of the protective film covering the element regions. The mixture has a solid component ratio of 200 g/L or more, and droplets of the sprayed mixture have an average particle size of 12 μm or less.