Invention Grant
- Patent Title: Method of manufacturing element chip
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Application No.: US16103025Application Date: 2018-08-14
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Publication No.: US10607846B2Publication Date: 2020-03-31
- Inventor: Hidehiko Karasaki , Noriyuki Matsubara , Atsushi Harikai , Hidefumi Saeki
- Applicant: Panasonic Intellectual Property Management Co., Ltd.
- Applicant Address: JP Osaka
- Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
- Current Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
- Current Assignee Address: JP Osaka
- Agency: Pearne & Gordon LLP
- Priority: JP2017-172366 20170907
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/3065 ; B23K26/0622 ; H01L21/02 ; H01L21/475 ; H01L21/67 ; H01L21/683 ; H01L21/78

Abstract:
Method of manufacturing an element chip which can suppress residual debris in plasma dicing. A back surface of a semiconductor wafer is held on a dicing tape. Then, a surface of the wafer is coated with a mask that includes a water-insoluble lower mask and a water-soluble upper mask. Subsequently, an opening is formed in the mask by irradiating the mask with laser light to expose a dividing region. Then, the semiconductor wafer is caused to come into contact with water to remove the upper mask covering each of the element regions while leaving the lower layer. After that, the wafer is exposed to plasma to perform etching on the dividing region exposed from the opening until the etching reaches the back surface, thereby dicing the semiconductor wafer into a plurality of element chips. Thereafter, the lower layer mask left on the front surface of the semiconductor chips is removed.
Public/Granted literature
- US20190074185A1 METHOD OF MANUFACTURING ELEMENT CHIP Public/Granted day:2019-03-07
Information query
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