公开(公告)号：US11335564B2

公开(公告)日：2022-05-17

申请号：US16993466

申请日：2020-08-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Akihiro Itou ,  Atsushi Harikai ,  Toshiyuki Takasaki ,  Shogo Okita

IPC: H01L21/3065 ,  H01L21/02

Abstract: An element chip smoothing method including: an element chip preparation step of preparing at least one element chip including a first surface covered with a resin film, a second surface opposite the first surface, and a sidewall connecting the first surface to the second surface and having ruggedness; a sidewall cleaning step of exposing the element chip to a first plasma, to remove deposits adhering to the sidewall, with the resin film allowed to continue to exist; a sidewall oxidation step of exposing the element chip to a second plasma, after the sidewall cleaning step, to oxidize a surface of the sidewall, with the resin film allowed to continue to exist; and a sidewall etching step of exposing the element chip to a third plasma, after the sidewall oxidation step, to etch the sidewall, with the resin film allowed to continue to exist.

公开(公告)号：US12205823B2

公开(公告)日：2025-01-21

申请号：US17550309

申请日：2021-12-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Toshiyuki Takasaki ,  Ryota Furukawa ,  Atsushi Harikai ,  Shogo Okita

IPC: H01L21/3065 ,  H01L21/311 ,  H01L21/78

Abstract: Disclosed is a method for producing element chips. The method includes: a preparing step of preparing a substrate 10 that is held on a holding sheet 22 that is supported by a frame 21, the substrate including element regions and dicing regions; a protective film forming step of forming a protective film 15 so as to cover the frame 21, the holding sheet 22, and the substrate 10; a patterning step of removing a part of the protective film 15 so as to expose the dicing regions of the substrate 10; a plasma dicing step including a process that uses a plasma that contains fluorine, the plasma dicing step being a step of individualizing the substrate 10 into a plurality of element chips; and a fluorine removing step of removing, together with the protective film 15, fluorine attached to the protective film 15 in the plasma dicing step.

公开(公告)号：US11219929B2

公开(公告)日：2022-01-11

申请号：US16896338

申请日：2020-06-09

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Akihiro Itou ,  Atsushi Harikai ,  Toshiyuki Takasaki ,  Hidefumi Saeki ,  Shogo Okita

IPC: B08B3/08 ,  B08B3/04

Abstract: An element chip cleaning method including: an element chip preparation step of preparing at least one element chip having a first surface and a second surface opposite the first surface, the first surface covered with a resin film; a first cleaning step of bringing a first cleaning liquid into contact with the resin film, the first cleaning liquid including a solvent that dissolves at least part of a resin component contained in the resin film; and a second cleaning step of spraying a second cleaning liquid against the resin film from the first surface side of the element chip, after the first cleaning step.

公开(公告)号：US12230541B2

公开(公告)日：2025-02-18

申请号：US17456914

申请日：2021-11-30

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Shogo Okita ,  Akihiro Itou ,  Toshiyuki Takasaki

IPC: H01L21/78 ,  H01L21/304 ,  H01L21/3065

Abstract: The element chip manufacturing method includes: a preparing process of preparing a substrate 1 including a plurality of element regions EA and a dividing region DA, the substrate 1 having a first principal surface 1X and a second principal surface 1Y; a groove forming process of forming a groove 13 in the dividing region DA from the first principal surface 1X side; and a grinding process of grinding the substrate 1 from the second principal surface 1Y side, to divide the substrate 1 into a plurality of element chips 20. The groove 13 includes a first region 13a constituted by a side surface having a first surface roughness, and a second region 13b constituted by a side surface having a second surface roughness larger than the first surface roughness. In the grinding process, grinding of the substrate 1 is performed until reaching the first region 13a of the groove 13.

公开(公告)号：US12165845B2

公开(公告)日：2024-12-10

申请号：US18056294

申请日：2022-11-17

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo Okita ,  Yoshiyuki Wada ,  Takahiro Miyai ,  Naoaki Takeda ,  Toshihiro Wada ,  Toshiyuki Takasaki

IPC: H01J37/32

Abstract: Disclosed is a plasma processing apparatus 10 including a chamber 11, a stage 12, a dielectric member 13, a cover 14, a gas introduction path 15, and an induction coil 16. The induction coil 16 includes a first induction coil 17 installed so as to overlap a central region R1 of the dielectric member 13, and a second induction coil 18 installed so as to overlap a peripheral region R2 outside the central region R1 of the dielectric member 13. The cover 14 has a first gas hole 14c formed at a position overlapping the central region R1 and a second gas hole 14d formed at a position overlapping the peripheral region R2. The gas introduction path 15 has a first gas introduction path 15a communicating with the first gas hole 14c and a second gas introduction path 15b communicating with the second gas hole 14d.