公开(公告)号：US09245845B2

公开(公告)日：2016-01-26

申请号：US14736625

申请日：2015-06-11

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Kazuhiro Kaibara ,  Hiroshige Hirano

IPC: H01L23/528 ,  H01L23/482 ,  H01L29/778 ,  H01L29/06 ,  H01L23/00 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L23/5283 ,  H01L23/4824 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L29/0696 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2924/00014 ,  H01L2924/2076 ,  H01L2924/00

Abstract: A semiconductor device includes a first wiring layer stacked over element electrodes above a silicon substrate and a second wiring layer stacked over the first wiring layer. The first wiring layer includes first source electrode wires and first drain electrode wires. The second wiring layer includes second source electrode wires and second drain electrode wires. The first wiring layer includes a first region and second regions. In the first region, each of the first source electrode wires and the first drain electrode wires is continuous. In each of the second regions, each of the first source electrode wires and the first drain electrode wires is discontinuous. Second source electrode wires and second drain electrode wires are arranged to alternately over the first regions and the second regions in one direction. External connection terminals are not connected over the second regions, and are connected over the first regions.

Abstract translation: 半导体器件包括层叠在硅衬底上的元件电极上的第一布线层和堆叠在第一布线层上的第二布线层。 第一布线层包括第一源电极布线和第一漏电极布线。 第二布线层包括第二源电极布线和第二漏电极布线。 第一布线层包括第一区域和第二区域。 在第一区域中，第一源极电极线和第一漏极电极线中的每一个是连续的。 在每个第二区域中，第一源极电极线和第一漏极电极线中的每一个是不连续的。 第二源极电极线和第二漏极电极布置成在一个方向上交替地在第一区域和第二区域上。 外部连接端子不连接在第二区域上，并且连接在第一区域上。

公开(公告)号：US11699751B2

公开(公告)日：2023-07-11

申请号：US17091302

申请日：2020-11-06

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidekazu Umeda ,  Kazuhiro Kaibara ,  Satoshi Tamura

IPC: H01L29/80 ,  H01L29/78 ,  H01L29/423 ,  H01L29/778 ,  H01L29/20 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L29/78 ,  H01L29/0661 ,  H01L29/2003 ,  H01L29/4238 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/06 ,  H01L29/10 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/20 ,  H01L29/41758 ,  H01L29/4236

Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 μm-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by, for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.

公开(公告)号：US09911843B2

公开(公告)日：2018-03-06

申请号：US14636149

申请日：2015-03-02

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidekazu Umeda ,  Kazuhiro Kaibara ,  Satoshi Tamura

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/20 ,  H01L29/78 ,  H01L29/423 ,  H01L29/778 ,  H01L29/417

CPC classification number: H01L29/78 ,  H01L29/06 ,  H01L29/0661 ,  H01L29/10 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/7786

Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 μm-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.

公开(公告)号：US09698096B2

公开(公告)日：2017-07-04

申请号：US14854071

申请日：2015-09-15

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hiroshige Hirano ,  Kazuhiro Kaibara

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L21/48

CPC classification number: H01L23/5226 ,  H01L21/48 ,  H01L23/53238 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L2224/02166 ,  H01L2224/02372 ,  H01L2224/03 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/4847 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/49107 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor device of the disclosure comprises: a first wiring disposed on a semiconductor substrate; a first insulating film disposed on the first wiring; a first via disposed in the first insulating film so as to be connected to the first wiring; a second wiring disposed on the first insulating film so as to be connected to the first wiring through the first via; a first organic insulating film disposed on the second wiring; a second via disposed in the first organic insulating film so as to be connected to the second wiring; a third wiring disposed on the first organic insulating film so as to be connected to the second wiring through the second via; and a second organic insulating film disposed on the first organic insulating film. A pad opening portion through which the third wiring is exposed is provided in the second organic insulating film, and the first via, the second via, the second wiring, and the third wiring are made of metal whose main component is copper.