公开(公告)号：US20240348775A1

公开(公告)日：2024-10-17

申请号：US18756664

申请日：2024-06-27

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Yusuke KATO

IPC: H04N19/105 ,  H04N19/176 ,  H04N19/182

CPC classification number: H04N19/105 ,  H04N19/176 ,  H04N19/182

Abstract: An encoder includes circuitry and memory connected to the circuitry. The circuitry, in operation: derives, as a first parameter, a total sum of absolute values of sums of horizontal gradient values respectively for pairs of relative pixel positions; derives, as a second parameter, a total sum of absolute values of sums of vertical gradient values respectively for the pairs of relative pixel positions; derives, as a third parameter, a total sum of horizontal-related pixel difference values respectively for the pairs of relative pixel positions; derives, as a fourth parameter, a total sum of vertical-related pixel difference values respectively for the pairs of relative pixel positions; derives, as a fifth parameter, a total sum of vertical-related sums of horizontal gradient values respectively for the pairs of relative pixel positions; and generates a prediction image to be used to encode the current block using the first, second, third, fourth, and fifth parameters.

公开(公告)号：US20240292032A1

公开(公告)日：2024-08-29

申请号：US18659567

申请日：2024-05-09

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Yusuke KATO ,  Takahiro NISHI ,  Tadamasa TOMA ,  Kiyofumi ABE

IPC: H04N19/61 ,  H04N19/103 ,  H04N19/13 ,  H04N19/136 ,  H04N19/176 ,  H04N19/46 ,  H04N19/70 ,  H04N19/91

CPC classification number: H04N19/61 ,  H04N19/13 ,  H04N19/176 ,  H04N19/46 ,  H04N19/70 ,  H04N19/91 ,  H04N19/103 ,  H04N19/136

Abstract: An encoder includes circuitry and memory. In both of a first type of residual coding where an orthogonal transform is applied to a current block and a second type of residual coding where the orthogonal transform is skipped, wherein when a number of CABAC processes is within an allowable range, the circuitry encodes coefficient information flags by CABAC, each of the coefficient information flags relating to a coefficient included in the current block; and otherwise, the circuitry skips the encoding of the coefficient information flags; and the circuitry encodes a remainder value of the coefficient with Golomb-Rice code when the coefficient information flags are encoded; and the circuitry encodes a value of the coefficient with the Golomb-Rice code when the plurality of coefficient information flags are not encoded, wherein the coefficient information flags are partially different between the first type of residual coding and the second type of residual coding.

公开(公告)号：US20240187617A1

公开(公告)日：2024-06-06

申请号：US18440292

申请日：2024-02-13

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie DRUGEON ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Yusuke KATO

IPC: H04N19/31

CPC classification number: H04N19/31

Abstract: An encoder includes circuitry, and memory coupled to the circuitry. The circuitry, in operation, for each of a plurality of sub-bitstreams having mutually different frame rates, encodes identification information into a header of a bitstream including the plurality of sub-bitstreams, the identification information indicating a temporal ID that is an identifier of a temporal layer related to a temporal scalability and corresponds to the sub-bitstream, and encodes level information indicating a conformance level of the sub-bitstream.

公开(公告)号：US20240007661A1

公开(公告)日：2024-01-04

申请号：US18368642

申请日：2023-09-15

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takahiro NISHI ,  Tadamasa TOMA ,  Kiyofumi ABE ,  Yusuke KATO

IPC: H04N19/44 ,  H04N19/119 ,  H04N19/176 ,  H04N19/70

CPC classification number: H04N19/44 ,  H04N19/119 ,  H04N19/176 ,  H04N19/70

Abstract: According to one aspect of the present disclosure, a decoder includes memory and a processor coupled to the memory. The processor is configured to split a current picture into tiles, generate a slice having a rectangular shape and located at a lower-right corner of the current picture, the slice including at least a part of a tile among the tiles, generate first information on a region of the slice with header information, the header information not including information identical to the first information, and decode the slice with the first information.

公开(公告)号：US20230353790A1

公开(公告)日：2023-11-02

申请号：US18052108

申请日：2022-11-02

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chu Tong WANG ,  Chong Soon LIM ,  Han Boon TEO ,  Hai Wei SUN ,  Jing Ya LI ,  Che-Wei KUO ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Yusuke KATO

IPC: H04N19/17 ,  H04N19/186 ,  H04N19/82 ,  H04N19/117 ,  H04N19/132 ,  H04N19/167

CPC classification number: H04N19/82 ,  H04N19/117 ,  H04N19/132 ,  H04N19/167 ,  H04N19/17 ,  H04N19/186

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in response to a first reconstructed image sample being located outside a virtual boundary, duplicates a reconstructed sample located inside and adjacent to the virtual boundary to generate the first reconstructed image sample. The circuitry generates a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to the first reconstructed image sample of a luma component. The circuitry generates a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component. The circuitry generates a third coefficient value by adding the first coefficient value to the second coefficient value, and encodes a third reconstructed image sample of the chroma component using the third coefficient value.

公开(公告)号：US20220337876A1

公开(公告)日：2022-10-20

申请号：US17727299

申请日：2022-04-22

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya LI ,  Che Wei KUO ,  Chong Soon LIM ,  Chu Tong WANG ,  Han Boon TEO ,  Hai Wei SUN ,  Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Yusuke KATO

IPC: H04N19/66 ,  H04N19/122 ,  H04N19/176

Abstract: An encoder determines, based on a width and a height of a block, whether or not to disable a prediction mode in which the block is split along a partitioning line defined by a distance and an angle and then prediction is performed; and encodes the block with the prediction mode disabled or not disabled according to a result of the determination on whether or not to disable the prediction mode. Here, the distance is the shortest distance between the center of the block and the partitioning line, and the angle is an angle representing a direction from the center of the block toward the partitioning line in the shortest distance. The encoder determines to disable the prediction mode when (i) a width-to-height ratio is at least 8 or (ii) a height-to-width ratio is at least 8.

公开(公告)号：US20220191487A1

公开(公告)日：2022-06-16

申请号：US17685226

申请日：2022-03-02

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Che-Wei KUO ,  Chong Soon LIM ,  Jing Ya LI ,  Han Boon TEO ,  Hai Wei SUN ,  Chu Tong WANG ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Yusuke KATO

IPC: H04N19/117 ,  H04N19/82 ,  H04N19/186 ,  H04N19/13 ,  H04N19/119 ,  H04N19/176 ,  H04N19/593 ,  H04N19/18 ,  H04N19/124 ,  H04N19/96 ,  H04N19/61

Abstract: An encoder includes circuitry and memory. The circuitry, in operation, generates a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to a first reconstructed image sample of a luma component. The circuitry generates a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component. The circuitry generates a third coefficient value by adding the first coefficient value to the second coefficient value, and encodes a third reconstructed image sample of the chroma component using the third coefficient value. The circuitry determines a first parameter having the same value for Cb component and Cr component of the chroma component. The circuitry determines, using the first parameter, a model of entropy coding from a plurality of models. The circuitry performs, using the model, the entropy coding of a second parameter of the CCALF process.

公开(公告)号：US20220150484A1

公开(公告)日：2022-05-12

申请号：US17583768

申请日：2022-01-25

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon LIM ,  Hai Wei SUN ,  Jing Ya LI ,  Han Boon TEO ,  Che-Wei KUO ,  Chu Tong WANG ,  Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Yusuke KATO

IPC: H04N19/117 ,  H04N19/82 ,  H04N19/132 ,  H04N19/169

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: encodes information for deriving a parameter into a header of a bitstream; filters reconstructed samples in a first image using a filtering process, to generate a second image; determines whether the parameter has a predefined value; encodes a third image using the second image when the parameter has the predefined value; and encodes the third image using the first image when the parameter does not have the predefined value.

公开(公告)号：US20220078462A1

公开(公告)日：2022-03-10

申请号：US17526098

申请日：2021-11-15

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Yusuke KATO

IPC: H04N19/46 ,  H04N19/184 ,  H04N19/65

Abstract: An encoder that includes memory and circuitry coupled to the memory. The circuitry encodes a slice into one or more data access regions in a variable length encoding process. The circuitry encodes one or more offsets into a slice header, based on a flag written into a sequence header and a total number of the one or more data access regions. The one or more offsets each specify a head position of a corresponding one of the one or more data access regions in a bitstream. When the flag indicates that the one or more offsets are to be encoded and the total number is at least two, the one or more offsets are encoded. The flag switches between encoding and not encoding the one or more offsets regardless of whether the total number is at least two.

公开(公告)号：US20220070500A1

公开(公告)日：2022-03-03

申请号：US17507571

申请日：2021-10-21

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya LI ,  Han Boon TEO ,  Chong Soon LIM ,  Hai Wei SUN ,  Che-Wei KUO ,  Chu Tong WANG ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Yusuke KATO

IPC: H04N19/82 ,  H04N19/107 ,  H04N19/176 ,  H04N19/186

Abstract: A decoder includes memory and a processor coupled to the memory and configured to: generate a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to a first reconstructed image sample of a luma component; clip the first coefficient value such that the clipped first coefficient value is within a first range from −27 to 27−1; generate a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component; clip the second coefficient value such that the clipped second coefficient value is within a second range different from the first range; generate a third coefficient value by adding the clipped first coefficient value to the clipped second coefficient value; and generate a third reconstructed image sample of the chroma component using the third coefficient value.