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    Thermally tempered glass substrate using CTE mismatched layers and paste mixtures for transient electronic systems
    3.
    发明授权
    Thermally tempered glass substrate using CTE mismatched layers and paste mixtures for transient electronic systems 有权
    使用CTE不匹配层和瞬态电子系统的糊状混合物的热钢化玻璃基板

    公开(公告)号：US09356603B2

    公开(公告)日：2016-05-31

    申请号：US14694121

    申请日：2015-04-23

    Applicant: Palo Alto Research Center Incorporated

    Inventor： Scott J. H. Limb ,  Gregory L. Whiting ,  Sean R. Garner

    IPC: H01L23/15 ,  C03C4/00 ,  H03K19/177 ,  B32B7/02 ,  B32B17/00 ,  C03B23/203 ,  C03B19/09 ,  C03C3/00 ,  H01L21/71 ,  H01L23/14 ,  H01L27/00

    CPC classification number: H03K19/17768 ,  B32B7/02 ,  B32B17/00 ,  B32B2457/08 ,  B32B2457/14 ,  C03B19/09 ,  C03B23/203 ,  C03C3/00 ,  C03C4/0064 ,  H01L21/71 ,  H01L23/14 ,  H01L23/15 ,  H01L23/57 ,  H01L27/00 ,  H01L27/12 ,  H01L2924/0002 ,  Y10T428/24942 ,  H01L2924/00

    Abstract: A thermally tempered glass substrate for transient electronic systems (i.e., including electronic devices that visually disappear when triggered to do so) including two or more fused-together glass structures having different coefficient of thermal expansion (CTE) values disposed in an intermixed arrangement manner that generates and stores potential energy in the form of residual, self-equilibrating internal stresses. In alternative embodiments the substrate includes laminated glass sheets, or glass elements (e.g., beads or cylinders) disposed in a glass layer. A trigger device causes an initial fracture in the thermally tempered glass substrate, whereby the fracture energy nearly instantaneously travels throughout the thermally tempered glass substrate, causing the thermally tempered glass substrate to shatter into multiple small (e.g., micron-sized) pieces that are difficult to detect. Patterned fracture features are optionally provided to control the final fractured particle size. Electronic systems built on the substrate are entirely destroyed and dispersed during the transience event.

    Abstract translation: 一种用于瞬态电子系统的热钢化玻璃基板（即，包括在触发时视觉上消失的电子设备），包括具有不同热膨胀系数（CTE）值的两个或更多个熔合在一起的玻璃结构，其以混合排列方式设置， 以残余的自平衡内应力的形式产生和存储势能。 在替代实施例中，衬底包括夹层玻璃片，或设置在玻璃层中的玻璃元件（例如，珠或圆筒）。 触发装置引起热钢化玻璃基板中的初始断裂，由此断裂能几乎瞬时地穿过热钢化玻璃基板，导致热钢化玻璃基板粉碎成难以进入的多个小（例如，微米级）的部件 检测。 可选地提供图案化的断裂特征以控制最终的断裂的粒度。 在基板上构建的电子系统在瞬态事件期间被完全破坏和分散。

    Solar cell texturing
    4.
    发明授权
    Solar cell texturing 有权
    太阳能电池纹理

    公开(公告)号：US08951825B1

    公开(公告)日：2015-02-10

    申请号：US14023423

    申请日：2013-09-10

    Applicant: Palo Alto Research Center Incorporated

    Inventor： Scott J. H. Limb ,  Dirk DeBruyker ,  Sean Garner

    IPC: H01L21/00 ,  H01L31/18 ,  H01L21/308

    CPC classification number: H01L31/18 ,  H01L21/308 ,  H01L31/02363 ,  H01L31/1804 ,  Y02E10/52 ,  Y02E10/547 ,  Y02P70/521

    Abstract: Multicrystalline silicon (mc-Si) solar cells having patterned light trapping structures (e.g., pyramid or trough features) are generated by printing a liquid mask material from an array of closely-spaced parallel elongated conduits such that portions of the mc-Si wafer are exposed through openings defined between the printed mask features. Closely spaced mask pattern features are achieved using an array of conduits (e.g., micro-springs or straight polyimide cantilevers), where each conduit includes a slit-type, tube-type or ridge/valley-type liquid guiding channel that extends between a fixed base end and a tip end of the conduit such that mask material supplied from a reservoir is precisely ejected from the tip onto the mc-Si wafer. The exposed planar surface portions are then etched to form the desired patterned light trapping structures (e.g., trough structures).

    Abstract translation: 通过从紧密间隔开的平行细长导管的阵列印刷液体掩模材料来产生具有图案化的光捕获结构（例如，金字塔或槽特征）的多晶硅（mc-Si）太阳能电池，使得mc-Si晶片的部分 通过印刷的掩模特征之间限定的开口露出。 使用导管阵列（例如微弹簧或直接聚酰亚胺悬臂）实现紧密间隔的掩模图案特征，其中每个导管包括狭缝型，管型或脊/谷型液体引导通道，其在固定 基端和管道的末端，使得从储存器供应的掩模材料从尖端精确地喷射到mc-Si晶片上。 然后对暴露的平面表面部分进行蚀刻以形成所需的图案化光捕获结构（例如槽结构）。

    Complex stress-engineered frangible structures
    5.
    发明授权
    Complex stress-engineered frangible structures 有权

    公开(公告)号：US10648491B2

    公开(公告)日：2020-05-12

    申请号：US16273397

    申请日：2019-02-12

    Applicant: Palo Alto Research Center Incorporated

    Inventor： Scott J. H. Limb ,  Gregory L. Whiting

    IPC: C03C21/00 ,  F16B1/00 ,  B32B17/00 ,  C03C27/06 ,  C03C27/10 ,  C03B27/00 ,  C03B23/203 ,  C03B23/20 ,  C03C15/00 ,  C03C27/04 ,  B32B17/10

    Abstract: A stress-engineered frangible structure includes multiple discrete glass members interconnected by inter-structure bonds to form a complex structural shape. Each glass member includes strengthened (i.e., by way of stress-engineering) glass material portions that are configured to transmit propagating fracture forces throughout the glass member. Each inter-structure bond includes a bonding member (e.g., glass-frit or adhesive) connected to weaker (e.g., untreated, unstrengthened, etched, or thinner) glass member region(s) disposed on one or both interconnected glass members that function to reliably transfer propagating fracture forces from one glass member to other glass member. An optional trigger mechanism generates an initial fracture force in a first (most-upstream) glass member, and the resulting propagating fracture forces are transferred by way of inter-structure bonds to all downstream glass members. One-way crack propagation is achieved by providing a weaker member region only on the downstream side of each inter-structure bond.

    Complex stress-engineered frangible structures
    6.
    发明授权
    Complex stress-engineered frangible structures 有权

    公开(公告)号：US10202990B2

    公开(公告)日：2019-02-12

    申请号：US16025573

    申请日：2018-07-02

    Applicant: Palo Alto Research Center Incorporated

    Inventor： Scott J. H. Limb ,  Gregory L. Whiting

    IPC: C03C21/00 ,  F16B1/00 ,  C03B27/00 ,  C03C27/10 ,  C03C27/06 ,  B32B17/00 ,  C03C27/04 ,  C03C15/00 ,  C03B23/203 ,  C03B23/20 ,  B32B17/10

    Abstract: A stress-engineered frangible structure includes multiple discrete glass members interconnected by inter-structure bonds to form a complex structural shape. Each glass member includes strengthened (i.e., by way of stress-engineering) glass material portions that are configured to transmit propagating fracture forces throughout the glass member. Each inter-structure bond includes a bonding member (e.g., glass-frit or adhesive) connected to weaker (e.g., untreated, unstrengthened, etched, or thinner) glass member region(s) disposed on one or both interconnected glass members that function to reliably transfer propagating fracture forces from one glass member to other glass member. An optional trigger mechanism generates an initial fracture force in a first (most-upstream) glass member, and the resulting propagating fracture forces are transferred by way of inter-structure bonds to all downstream glass members. One-way crack propagation is achieved by providing a weaker member region only on the downstream side of each inter-structure bond.

    Stressed Substrates For Transient Electronic Systems
    7.
    发明申请
    Stressed Substrates For Transient Electronic Systems 有权
    用于瞬态电子系统的强化衬底

    公开(公告)号：US20150102852A1

    公开(公告)日：2015-04-16

    申请号：US14052348

    申请日：2013-10-11

    Applicant: Palo Alto Research Center Incorporated

    Inventor： Scott J. H. Limb ,  Gregory L. Whiting ,  Sean R. Garner ,  JengPing Lu ,  Dirk DeBruyker

    IPC: H03K19/177

    CPC classification number: H03K19/17768 ,  H01L21/64 ,  H01L21/71 ,  H01L23/14 ,  H01L23/57 ,  H01L27/00 ,  H01L27/12 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A stressed substrate for transient electronic systems (i.e., electronic systems that visually disappear when triggered to do so) that includes one or more stress-engineered layers that store potential energy in the form of a significant internal stress. An associated trigger mechanism is also provided that, when triggered, causes an initial fracture in the stressed substrate, whereby the fracture energy nearly instantaneously travels throughout the stressed substrate, causing the stressed substrate to shatter into multiple small (e.g., micron-sized) pieces that are difficult to detect. The internal stress is incorporated into the stressed substrate through strategies similar to glass tempering (for example through heat or chemical treatment), or by depositing thin-film layers with large amounts of stress. Patterned fracture features are optionally provided to control the final fractured particle size. Electronic systems built on the substrate are entirely destroyed and dispersed during the transience event.

    Abstract translation: 用于瞬态电子系统的应力衬底（即，当触发时视觉消失的电子系统）包括一个或多个以显着的内部应力的形式存储势能的应力设计层。 还提供了一种相关联的触发机构，其在被触发时引起应力基底中的初始断裂，由此断裂能几乎瞬时地穿过受压基底，导致受应力的基底碎裂成多个小（例如，微米级） 这很难发现。 通过与玻璃回火（例如通过热或化学处理）相似的策略，或者通过沉积具有大量应力的薄膜层，将内部应力结合到受压基板中。 可选地提供图案化的断裂特征以控制最终的断裂的粒度。 在基板上构建的电子系统在瞬态事件期间被完全破坏和分散。

    Transient electronic device with ion-exchanged glass treated interposer
    8.
    发明授权
    Transient electronic device with ion-exchanged glass treated interposer 有权

    公开(公告)号：US10541215B1

    公开(公告)日：2020-01-21

    申请号：US16385452

    申请日：2019-04-16

    Applicant: Palo Alto Research Center Incorporated

    Inventor： Scott J. H. Limb ,  Gregory L. Whiting

    IPC: H01L23/495 ,  H01L23/00 ,  H01L23/15 ,  H01L21/48 ,  H01L23/498 ,  H01L25/065

    Abstract: A transient electronic device utilizes a glass-based interposer that is treated using ion-exchange processing to increase its fragility, and includes a trigger device operably mounted on a surface thereof. An integrated circuit (IC) die is then bonded to the interposer, and the interposer is mounted to a package structure where it serves, under normal operating conditions, to operably connect the IC die to the package I/O pins/balls. During a transient event (e.g., when unauthorized tampering is detected), a trigger signal is transmitted to the trigger device, causing the trigger device to generate an initial fracture force that is applied onto the glass-based interposer substrate. The interposer is configured such that the initial fracture force propagates through the glass-based interposer substrate with sufficient energy to both entirely powderize the interposer, and to transfer to the IC die, whereby the IC die also powderizes (i.e., visually disappears).

    Stressed substrates for transient electronic systems
    9.
    再颁专利
    Stressed substrates for transient electronic systems 有权

    公开(公告)号：USRE47570E1

    公开(公告)日：2019-08-13

    申请号：US15726944

    申请日：2017-10-06

    Applicant: Palo Alto Research Center Incorporated

    Inventor： Scott J. H. Limb ,  Gregory L. Whiting ,  Sean R. Garner ,  JengPing Lu ,  Dirk De Bruyker

    IPC: H01L21/64 ,  H01L21/71 ,  H01L23/14 ,  H01L27/00 ,  H03K19/177

    Abstract: A stressed substrate for transient electronic systems (i.e., electronic systems that visually disappear when triggered to do so) that includes one or more stress-engineered layers that store potential energy in the form of a significant internal stress. An associated trigger mechanism is also provided that, when triggered, causes an initial fracture in the stressed substrate, whereby the fracture energy nearly instantaneously travels throughout the stressed substrate, causing the stressed substrate to shatter into multiple small (e.g., micron-sized) pieces that are difficult to detect. The internal stress is incorporated into the stressed substrate through strategies similar to glass tempering (for example through heat or chemical treatment), or by depositing thin-film layers with large amounts of stress. Patterned fracture features are optionally provided to control the final fractured particle size. Electronic systems built on the substrate are entirely destroyed and dispersed during the transience event.

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