公开(公告)号：US20050024133A1

公开(公告)日：2005-02-03

申请号：US10629203

申请日：2003-07-29

申请人： Pallab Midya ,  Steven Bergstedt ,  William Roeckner

发明人： Pallab Midya ,  Steven Bergstedt ,  William Roeckner

IPC分类号： H03F1/32 ,  H03F3/185 ,  H03F3/217 ,  H03F3/38

CPC分类号： H03F3/2173 ,  H03F1/32 ,  H03F1/3247 ,  H03F3/185 ,  H03F3/2171

摘要： Disclosed is a method and/or apparatus for adjusting the sample time and order associated with a digital correction system for maximizing output power and minimizing power stage delay sensitivity of a switching power stage. In certain embodiments, the sample point of an ADC may be changed as a function of the duty ratio of the PWM signal thus allowing higher performance and use of less expensive power stage components. In addition, adjustment of the order of an integrating error amplifier in the system permits operation of the power stage with an output being permitted to saturate up to the power supply rails, thus increasing a power output of the power stage.

公开(公告)号：US20070109165A1

公开(公告)日：2007-05-17

申请号：US11273286

申请日：2005-11-14

申请人： Pallab Midya ,  William Roeckner ,  John Grosspietsch ,  Anthony Schooler

发明人： Pallab Midya ,  William Roeckner ,  John Grosspietsch ,  Anthony Schooler

IPC分类号： H03M1/66

CPC分类号： H03M3/366 ,  H03M3/432 ,  H03M3/452

摘要： An audio amplifier includes a digital signal processor (DSP) that contains a noise shaping quantizer having an integrating error amplifier. The integrating error amplifier contains integrators connected in a feedback loop, a summer supplied with an output of each of the integrators, and a saturation function module producing a saturation function. A multiplier is disposed between each pair of adjacent integrators. The multiplier receives a signal from one of the adjacent integrators and the saturation function and supplies a signal to the other of the adjacent integrators. The saturation function decreases the effect of all of the integrators except an integrator to which an input signal to the integrating amplifier is supplied using an input signal to and/or an output signal from the noise shaping quantizer. This permits the duty ratio of the output signal from the noise shaping quantizer to extend from 0% to 100%.

摘要翻译： 音频放大器包括包含具有积分误差放大器的噪声整形量化器的数字信号处理器（DSP）。 积分误差放大器包含连接在反馈回路中的积分器，与每个积分器的输出相加的夏季以及产生饱和功能的饱和功能模块。 在每对相邻的积分器之间设置乘法器。 乘法器接收来自相邻积分器之一的信号和饱和度函数，并向相邻的积分器中的另一个提供信号。 饱和功能降低了除了积分器之外的所有积分器的影响，使用来自噪声整形量化器的输入信号和/或来自噪声整形量化器的输出信号向积分放大器提供输入信号。 这允许来自噪声整形量化器的输出信号的占空比从0％延伸到100％。

公开(公告)号：US06819912B2

公开(公告)日：2004-11-16

申请号：US10008121

申请日：2001-11-05

申请人： William Roeckner ,  Pallab Midya ,  Gregory Buchwald

发明人： William Roeckner ,  Pallab Midya ,  Gregory Buchwald

IPC分类号： H03F338

CPC分类号： H03F3/2171 ,  H04B15/04

摘要： A switching amplifier generates noise at its switching frequency and harmonics thereof. The noise at these harmonics, for an audio amplifier, will be generated with significant amplitude in the AM band. Thus, an AM tuner will experience interference problems if the tuner frequency is sufficiently close to one of these harmonics. To avoid this problem the switching frequency of the switching amplifier is chosen based on the tuner frequency. Thus, the switching frequency is chosen to avoid having harmonics at or too near the chosen tuner frequency. The switching amplifier is disabled when the tuner is in seek or scan mode. Instead of using the tuner frequency to determine what switching frequency should be used to avoid interference, the interference can be detected directly to cause a change in the switching frequency and thus remove the interference.

摘要翻译： 开关放大器以其开关频率和谐波产生噪声。 对于音频放大器，这些谐波的噪声将在AM频带中以显着的幅度产生。 因此，如果调谐器频率足够接近这些谐波之一，则AM调谐器将经历干扰问题。 为了避免这个问题，基于调谐器频率来选择开关放大器的开关频率。 因此，选择开关频率以避免在所选择的调谐器频率处或谐波附近。 当调谐器处于寻线或扫描模式时，开关放大器被禁止。 不是使用调谐器频率来确定应该使用什么开关频率来避免干扰，所以可以直接检测干扰，导致开关频率的变化，从而消除干扰。

公开(公告)号：US06605991B2

公开(公告)日：2003-08-12

申请号：US09943177

申请日：2001-08-30

申请人： Pallab Midya ,  William Roeckner

发明人： Pallab Midya ,  William Roeckner

IPC分类号： H03F338

CPC分类号： H03F3/2173 ,  H03F3/2171 ,  H03F2200/342 ,  H03F2200/345 ,  H03F2200/351

摘要： A modulated signal is connected to a full bridge switching amplifier (16, 18, 28, 30) and is compensated to remove a predetermined frequency and its odd harmonics. The compensation inverts and delays (26) a signal that is connected to a first half of the full bridge and applies the delayed inverted signal to a second half of the full bridge. By delaying by an odd number of half cycles, the carrier and its odd harmonics are cancelled because the same signal exists on both sides of the full bridge output. When these two same signals are subtracted by the full bridge action, the carrier and odd harmonics are suppressed. Spectral nulls may be provided for various signal applications, not just audio, and when various types of modulation techniques are used, such as PWM and PDM.

摘要翻译： 调制信号连接到全桥开关放大器（16,18,28,30），并被补偿以去除预定频率及其奇次谐波。 补偿反相并延迟（26）连接到全桥的前半部分的信号，并将延迟的反相信号施加到全桥的后半部分。 通过延迟奇数半周期，载波及其奇次谐波被消除，因为在全桥输出的两侧存在相同的信号。 当通过全桥动作减去这两个相同的信号时，载波和奇次谐波被抑制。 可以为各种信号应用（不仅仅是音频）以及当使用各种类型的调制技术（例如PWM和PDM）时提供频谱零点。

公开(公告)号：US20070139103A1

公开(公告)日：2007-06-21

申请号：US11314203

申请日：2005-12-20

申请人： William Roeckner ,  Pallab Midya ,  Patrick Rakers ,  Lawrence Connell ,  Daniel Mavencamp ,  Bradley Stewart

发明人： William Roeckner ,  Pallab Midya ,  Patrick Rakers ,  Lawrence Connell ,  Daniel Mavencamp ,  Bradley Stewart

IPC分类号： H03F3/38

CPC分类号： H03F3/2173 ,  H03F1/305 ,  H03F3/2171 ,  H03F3/72 ,  H03F2200/03 ,  H03F2200/351 ,  H03K17/161

摘要： A closed loop audio amplifier system and method of powering up/down the system without producing audible artifacts are provided. During power up, a prebias voltage is provided to each output connected to a speaker to increase the voltage to a nominal output level. High impedance switches are then driven at a 50% duty cycle. Feedback from the output is supplied to a servo, which is enabled to fine tune the output voltage. Low impedance switches are then driven at a 50% duty cycle at a quarter cycle timing. The order of the feedback loop depends on which of the high or low impedance switches are driven. The prebias voltage is then removed before audio signals to be amplified are supplied to the system. Timing of driving of the switches is programmable. To power down,. essentially the reverse sequence is provided.

摘要翻译： 提供一种闭环音频放大器系统以及在不产生可听见的伪影的情况下对系统加电/下电的方法。 在上电期间，向连接到扬声器的每个输出端提供预偏置电压以将电压增加到额定输出电平。 然后以50％占空比驱动高阻抗开关。 输出端的反馈信号被提供给一个伺服控制器，可以对输出电压进行微调。 然后，在四分之一周期的时间，以50％的占空比驱动低阻抗开关。 反馈环路的顺序取决于驱动高阻抗或低阻抗开关中的哪一个。 然后在将要放大的音频信号提供给系统之前，去除预偏置电压。 开关的驱动时序是可编程的。 断电 基本上提供了相反的顺序。

公开(公告)号：US5995033A

公开(公告)日：1999-11-30

申请号：US17617

申请日：1998-02-02

申请人： William Roeckner ,  Neal Hollenbeck ,  Timothy Rueger ,  Walter Czarnocki

发明人： William Roeckner ,  Neal Hollenbeck ,  Timothy Rueger ,  Walter Czarnocki

IPC分类号： H03M1/10 ,  H03M1/02 ,  H03M1/38 ,  H03M1/46 ,  H03M1/66 ,  H03M1/12 ,  H03M1/06

CPC分类号： H03M1/02 ,  G01D3/021 ,  G01D3/022 ,  H03M1/1019 ,  H03M1/46 ,  H03M1/662

摘要： An electronically calibrated sensor (100) includes a sensing element (102) with an output coupled to a signal conditioning circuit (104). The signal conditioning circuit (104) is adapted to be highly computationally efficient and operable for compensating for temperature and part-to-part variation on the sensing element output for providing a useable sensor output signal. The signal conditioning circuit (104) includes an analog-to-digital/digital-to-analog (ADC/DAC) conversion device (112). The ADC/DAC (112) is operable to perform both analog input signal analog-to-digital conversion and digital output signal digital-to-analog conversion. The ADC/DAC (112) is further adapted to provide analog control signals to input signal conditioning circuits (104, 106).

摘要翻译： 电子校准传感器（100）包括具有耦合到信号调理电路（104）的输出的感测元件（102）。 信号调理电路（104）适于高度计算效率并且可操作用于补偿感测元件输出端上的温度和部件间变化，以提供可用的传感器输出信号。 信号调理电路（104）包括模数/数/模（ADC / DAC）转换装置（112）。 ADC / DAC（112）可操作以执行模拟输入信号模数转换和数字输出信号数模转换。 ADC / DAC（112）还适于向输入信号调理电路（104,106）提供模拟控制信号。

公开(公告)号：US5939693A

公开(公告)日：1999-08-17

申请号：US17463

申请日：1998-02-02

申请人： William Roeckner ,  Timothy Rueger ,  Walter Czarnocki

发明人： William Roeckner ,  Timothy Rueger ,  Walter Czarnocki

IPC分类号： G06G7/20 ,  G06F7/544 ,  G06F17/10 ,  G06F11/10

CPC分类号： G06F7/5443

摘要： A polynomial calculator device is applied to calibrate a sensing device. Preferably the sensing device (100) includes a sensing element (102) with an output coupled to a signal conditioning circuit (104). The signal conditioning circuit (104) is adapted to be highly computationally efficient and operable for compensating for temperature and part-to-part variation on the sensing element output for providing a useable sensor output signal. A calibration method relies on a unique polynomial calculator (118) that is implemented as part of the signal conditioning circuit (104). The sensor is preferably manufactured and packaged prior to calibration so as to avoid any post-calibration processing error. The packaged sensor is calibrated and a number of calibration values are retained in a memory (114) and accessed by the calibration method during sensing element signal processing.

摘要翻译： 应用多项式计算器装置校准感测装置。 优选地，感测装置（100）包括具有耦合到信号调节电路（104）的输出的感测元件（102）。 信号调理电路（104）适于高度计算效率并且可操作用于补偿感测元件输出端上的温度和部件间变化，以提供可用的传感器输出信号。 校准方法依赖于被实现为信号调理电路（104）的一部分的唯一多项式计算器（118）。 传感器优选在校准之前制造和封装，以避免任何后校准处理错误。 校准了封装的传感器，并且在感测元件信号处理期间，通过校准方法将多个校准值保留在存储器（114）中并被校准方法访问。

公开(公告)号：US20070181981A1

公开(公告)日：2007-08-09

申请号：US11349608

申请日：2006-02-08

申请人： Neal Hollenbeck ,  Kenneth Haddad ,  William Roeckner

发明人： Neal Hollenbeck ,  Kenneth Haddad ,  William Roeckner

IPC分类号： H01L23/552

CPC分类号： H01L23/585 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An edge seal structure and fabrication method are described. The edge seal structure includes a high impedance substrate containing a base material and a grounded floating edge seal that is on the substrate but is isolated from the base material. The edge seal contacts a first doped well in the substrate that has the same conductivity type as and is more heavily doped than the base material. The first doped well is in a second doped well that has a different conductivity type than the first doped well. The first and second doped wells and the base material form back-to-back series connected diodes. The wells are effectively connected to power and ground such that the diodes are reverse-biased. The edge seal is formed by a stack of conductive layers, at least some of which are surrounded by a stack of insulating layers.

摘要翻译： 描述了边缘密封结构和制造方法。 边缘密封结构包括含有基材的高阻抗衬底和位于衬底上但与基底材料隔离的接地浮动边缘密封。 边缘密封接触衬底中的第一掺杂阱，其具有与基底材料相同的导电类型和比基底材料更重的掺杂。 第一掺杂阱位于具有与第一掺杂阱不同的导电类型的第二掺杂阱中。 第一和第二掺杂阱和基体材料形成背对背串联连接的二极管。 这些阱有效地连接到电源和接地，使得二极管被反向偏置。 边缘密封由一叠导电层形成，其中至少一些被一叠绝缘层包围。

公开(公告)号：US6041007A

公开(公告)日：2000-03-21

申请号：US17393

申请日：1998-02-02

申请人： William Roeckner

发明人： William Roeckner

IPC分类号： G11C16/02 ,  G11C16/22 ,  G11C7/00

CPC分类号： G11C16/22

摘要： A device, preferably an electronically calibrated sensor (100) includes a sensing element (102) with an output coupled to a calibration circuit (104). The calibration circuit (104) includes an electronically erasable programmable read only memory (EEPROM) (114). An EEPROM fuse (204) is employed in association with the EEPROM (114) which in a programming-disable logical state disables the write/erase program logic (208). The EEPROM fuse (204) may only be erased upon a valid fuse override signal (232) the input for which (224) in a final packaged device is inaccessible.

摘要翻译： 优选地，电子校准传感器（100）的装置包括具有耦合到校准电路（104）的输出的感测元件（102）。 校准电路（104）包括电子可擦除可编程只读存储器（EEPROM）（114）。 与EEPROM（114）相关联地使用EEPROM熔丝（204），在EEPROM的编程禁止逻辑状态下禁止写/擦除程序逻辑（208）。 EEPROM熔丝（204）只能在有效的保险丝超控信号（232）上被擦除，对于最终的封装设备（224）的输入是不可访问的。