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公开(公告)号：US11817869B2
公开(公告)日：2023-11-14
申请号：US17696579
申请日：2022-03-16
Applicant: NXP B.V.
Inventor： Ulrich Moehlmann , Steffen Rode , Ralf Gero Pilaski
CPC classification number: H03L7/0992 , H03L7/093 , H03L2207/50
Abstract: A control system for a digitally controlled oscillator with temperature compensation including a loop detector providing an error value, filter circuitry providing a lower resolution digital value to the DCO to generate an output oscillation signal at a frequency within a lower resolution range, tracking circuitry holding a tracking digital value at a tracking offset from center of a tracking range while the lower resolution digital value is being determined, and then regulating the frequency within a higher resolution range by adjusting the tracking digital value, temperature compensation circuitry performing temperature compensation steps to maintain the tracking digital value between first and second thresholds within the predetermined tracking range, and a controller configured to set the first and second thresholds within a narrow range around the tracking offset during a standard operating mode, and to adjust one or both thresholds within a wide range during a critical operating mode.
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公开(公告)号：US11658666B1
公开(公告)日：2023-05-23
申请号：US17708681
申请日：2022-03-30
Applicant: NXP B.V.
Inventor： Ulrich Moehlmann , Kai Hendrik Misselwitz
CPC classification number: H03L7/0818 , H03L7/083 , H03L7/093 , H03L7/0991 , H03L2207/50
Abstract: A fractional-N all digital phase locked loop (ADPLL) includes a randomly modulated delay having a triangular distribution to a frequency reference at an input of the fractional-n ADPLL to reduce spurious tones introduced by delta-sigma modulation of a frequency control word without requiring active control or calibration. In some embodiments, a delay line generates the randomly modulated delay based on a uniformly distributed random number with a flat spectrum that is shaped by a high pass filter.
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公开(公告)号：US20160344538A1
公开(公告)日：2016-11-24
申请号：US15156584
申请日：2016-05-17
Applicant: NXP B.V.
Inventor： Ulrich Moehlmann
CPC classification number: H04L7/0331 , H03L7/091 , H03L7/093 , H03L7/0991 , H03L2207/50 , H04B1/12
Abstract: A phase locked loop, comprising: a phase detector configured to determine a phase difference between a reference signal and a feedback signal; a loop filter configured to perform a filtering operation on a signal derived from the phase difference, and to provide a control signal; a frequency controlled oscillator configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal; wherein a low-pass filter is provided between the phase detector and the loop filter and/or between the loop filter and the frequency controlled oscillator to reduce quantization noise from the phase detector.
Abstract translation: 一种锁相环，包括：相位检测器，被配置为确定参考信号和反馈信号之间的相位差; 环路滤波器，被配置为对从所述相位差导出的信号执行滤波操作，并提供控制信号; 频率控制振荡器，被配置为接收所述控制信号并提供具有根据所述控制信号而变化的频率的输出信号; 其中在相位检测器和环路滤波器之间和/或环路滤波器和频率控制振荡器之间提供低通滤波器以减少来自相位检测器的量化噪声。
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公开(公告)号：US20160344396A1
公开(公告)日：2016-11-24
申请号：US15080222
申请日：2016-03-24
Applicant: NXP B.V.
Inventor： Ulrich Moehlmann
CPC classification number: H03L7/095 , H03L7/093 , H03L7/0991 , H03L2207/50
Abstract: A phase locked loop is disclosed comprising: a phase detector, loop filter and a frequency controlled oscillator. The phase detector is configured to determine a phase difference between a reference signal and a feedback signal. The loop filter is configured to perform a filtering operation on a signal derived from the phase difference and to provide a control signal. The frequency controlled oscillator is configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal. The phase locked loop further comprises a lock detector, including: a phase lock detector configured to receive a first signal from the phase locked loop, and to derive a phase lock signal from the first signal; a frequency lock detector configured to receive a second signal from the phase locked loop, and to derive a frequency lock signal from the second signal. An unlock detector may be provided, configured to determine whether the first signal has changed by a predetermined amount during a predetermined period.
Abstract translation: 公开了一种锁相环，包括：相位检测器，环路滤波器和频率控制振荡器。 相位检测器被配置为确定参考信号和反馈信号之间的相位差。 环路滤波器被配置为对从相位差导出的信号执行滤波操作并提供控制信号。 频率控制振荡器被配置为接收控制信号并提供具有根据控制信号而变化的频率的输出信号。 锁相环还包括锁定检测器，包括：锁相检测器，被配置为从锁相环接收第一信号，并从第一信号导出锁相信号; 频率锁定检测器，被配置为从锁相环接收第二信号，并从第二信号导出频率锁定信号。 可以提供解锁检测器，其被配置为在预定时段期间确定第一信号是否已经改变预定量。
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5.发明公开公开(公告)号：US20230299777A1
公开(公告)日：2023-09-21
申请号：US17696579
申请日：2022-03-16
Applicant: NXP B.V.
Inventor： Ulrich Moehlmann , Steffen Rode , Ralf Gero Pilaski
CPC classification number: H03L7/0992 , H03L7/093 , H03L2207/50
Abstract: A control system for a digitally controlled oscillator with temperature compensation including a loop detector providing an error value, filter circuitry providing a lower resolution digital value to the DCO to generate an output oscillation signal at a frequency within a lower resolution range, tracking circuitry holding a tracking digital value at a tracking offset from center of a tracking range while the lower resolution digital value is being determined, and then regulating the frequency within a higher resolution range by adjusting the tracking digital value, temperature compensation circuitry performing temperature compensation steps to maintain the tracking digital value between first and second thresholds within the predetermined tracking range, and a controller configured to set the first and second thresholds within a narrow range around the tracking offset during a standard operating mode, and to adjust one or both thresholds within a wide range during a critical operating mode.
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Patent Agency Ranking
公开(公告)号：US11218153B1
公开(公告)日：2022-01-04
申请号：US17084525
申请日：2020-10-29
Applicant: NXP B.V.
Inventor： Ulrich Moehlmann , Lars Henrik Heinbockel , Torsten Gerhardt , Christian Scherner
IPC: H03L7/099 , G01R31/3187 , H03L7/093
Abstract: A built-in self-test (BIST) block is provided that is incorporated into an all-digital phase locked loop (ADPLL) located on chip with the ADPLL. The BIST performs testing functions without need for support external to the chip. Test setup, test control, and test evaluation are performed entirely on chip. The BIST provides information regarding success or failure of the testing and can provide error information regarding test cases that do not pass successfully.
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公开(公告)号：US10396974B1
公开(公告)日：2019-08-27
申请号：US16041027
申请日：2018-07-20
Applicant: NXP B.V.
Inventor： Jan-Peter Schat , Ulrich Moehlmann
Abstract: An apparatus includes signal control circuitry, a phase-locked loop (PLL), and a correlation circuit. The signal control circuitry provides a reference clock signal carrying pseudo-random phase noise and as derived from an application clock signal and pseudo-random noise. The PLL, responsive to the reference clock signal carrying the pseudo-random phase noise, provides an output signal that is related to the phase of the reference clock signal. The correlation circuit self-tests the PLL by cross-correlating a signal corresponding to the output signal from the phase detector with the pseudo-random noise and, in response, by assessing results of the cross-correlation relative to a known threshold indicative of a performance level of the PLL.
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公开(公告)号：US20160036454A1
公开(公告)日：2016-02-04
申请号：US14446568
申请日：2014-07-30
Applicant: NXP B.V.
Inventor： Ulrich Moehlmann
IPC: H03L7/099
CPC classification number: H03L7/0994 , H03L7/099 , H03L7/0991 , H03L7/104 , H03L2207/06 , H03L2207/50
Abstract: Settling time may be reduced or eliminated for a phase-locked loop (ADPLL). An oscillator model provides proper settings that are applied to compensate both the frequency response and the phase response. A hardware device may include a Digital Controlled Oscillator (DCO); and a DCO model device with a processor, wherein the processor is configured to calculate a frequency for the DCO by searching for the frequency based upon operational parameters of the DCO, compare the calculated frequency to a measured frequency, and compensate, based upon the comparison, an ADPLL to decrease a settling time.
Abstract translation: 锁相环（ADPLL）可以减少或消除建立时间。 振荡器模型提供适用于补偿频率响应和相位响应的适当设置。 硬件设备可以包括数字控制振荡器（DCO）; 以及具有处理器的DCO模型设备，其中所述处理器被配置为通过基于所述DCO的操作参数搜索所述频率来计算所述DCO的频率，将所计算的频率与测量的频率进行比较，并且基于所述比较来补偿 ，ADPLL来减少建立时间。
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公开(公告)号：US11689206B1
公开(公告)日：2023-06-27
申请号：US17686664
申请日：2022-03-04
Applicant: NXP B.V.
Inventor： Ulrich Moehlmann , Andreas Lentz
IPC: H03L7/099
CPC classification number: H03L7/099 , H03L2207/50
Abstract: A method for clock frequency monitoring for a Phase-Locked Loop (PLL) based design includes determining a present operating point of an oscillator of the PLL based design, wherein the oscillator generates a present frequency in response to the present operating point. The present operating point of the oscillator is compared to a comparison range defined by a plurality of reference operating points, wherein the oscillator generates a nominal reference frequency in response to a nominal one of the plurality of reference operating points and the comparison range is further defined by a manufacturing process range, an operating voltage range and an operating temperature range. An action is performed in response to the present operating point being outside of the comparison range.
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公开(公告)号：US20220187423A1
公开(公告)日：2022-06-16
申请号：US17451567
申请日：2021-10-20
Applicant: NXP B.V.
Inventor： Ulrich Moehlmann , Jan-Peter Schat , Tim Lauber
IPC: G01S7/40 , H03L7/099 , H03L7/093 , G01S13/931
Abstract: The disclosure relates to monitoring of feedback systems such as phase lock loops. A system is disclosed, comprising: a feedback circuit (100); and a monitoring module (190). The monitoring module (190) is configured to: i) receive actual values of at least one state variable describing the state of the feedback circuit at a first time; ii) determine a predicted future value of the at least one state variable at a second time from the actual values at the first time using a model of the feedback circuit; iii) receive actual values of the at least one state variable at the second time; iv) compare the predicted future value of the at least one state variable at the second time with the actual value of the at least one state variable at the second time; and v) determine whether the feedback circuit has a fault condition, depending on the results of step iv).
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