公开(公告)号：US11218153B1

公开(公告)日：2022-01-04

申请号：US17084525

申请日：2020-10-29

Applicant: NXP B.V.

Inventor： Ulrich Moehlmann ,  Lars Henrik Heinbockel ,  Torsten Gerhardt ,  Christian Scherner

IPC: H03L7/099 ,  G01R31/3187 ,  H03L7/093

Abstract: A built-in self-test (BIST) block is provided that is incorporated into an all-digital phase locked loop (ADPLL) located on chip with the ADPLL. The BIST performs testing functions without need for support external to the chip. Test setup, test control, and test evaluation are performed entirely on chip. The BIST provides information regarding success or failure of the testing and can provide error information regarding test cases that do not pass successfully.

公开(公告)号：US10826505B1

公开(公告)日：2020-11-03

申请号：US16449711

申请日：2019-06-24

Applicant: NXP B.V.

Inventor： Ulrich Moehlmann ,  Andreas Johannes Köllmann ,  Christian Scherner

IPC: H03L7/099 ,  G04F10/00 ,  H03L7/093

Abstract: A hardware device includes a frequency lock loop (FLL) that includes a phase loop filter, and a phase lock loop (PLL) such as an all digital PLL (ADPLL) that includes a frequency loop filter. A controller provides a first control signal to the FLL and a second control signal to the PLL when the device operates the same. The device can also include a digital controlled oscillator (DCO) and part of one or more of the FLL and the PLL. The FLL and the PLL include first and second filters, respectively. The filters are coupled to the DCO. A time-to-digital converter (TDC) and a divider receive an input from the DCO. The controller forms a first loop with the first filter, the TDC, and the divider, and the controller forms a second loop with the second filter, the TDC, and the divider.