公开(公告)号：US11658666B1

公开(公告)日：2023-05-23

申请号：US17708681

申请日：2022-03-30

Applicant: NXP B.V.

Inventor： Ulrich Moehlmann ,  Kai Hendrik Misselwitz

IPC: H03L7/099 ,  H03L7/081 ,  H03L7/093 ,  H03L7/083

CPC classification number: H03L7/0818 ,  H03L7/083 ,  H03L7/093 ,  H03L7/0991 ,  H03L2207/50

Abstract: A fractional-N all digital phase locked loop (ADPLL) includes a randomly modulated delay having a triangular distribution to a frequency reference at an input of the fractional-n ADPLL to reduce spurious tones introduced by delta-sigma modulation of a frequency control word without requiring active control or calibration. In some embodiments, a delay line generates the randomly modulated delay based on a uniformly distributed random number with a flat spectrum that is shaped by a high pass filter.