公开(公告)号：US20120101782A1

公开(公告)日：2012-04-26

申请号：US13113061

申请日：2011-05-22

Applicant: Tsung-I Wang ,  Ming-Chieh Lin ,  Ching-Lin Lee

Inventor： Tsung-I Wang ,  Ming-Chieh Lin ,  Ching-Lin Lee

IPC: G06F15/00

CPC classification number: H02S50/10

Abstract: The invention employs a group of LED devices as a light source for emitting light with different wavelengths towards the solar cell under test. A set of test signal data composed of mutually orthogonal test signals are used to power the LED devices to emit light. The solar cell, upon receiving light from the LED devices powered by the test signal data, generates detected values which are in turn converted into electric signals. A processor device is then used to separate component signals contributed by the respective LED devices from the signals and compare the component signals to the output power level corresponding to the test signal data and/or to the optical energy levels radiated from the respective LED devices, thereby obtaining the spectral response of the solar cell to the different wavelengths of light.

Abstract translation: 本发明采用一组LED器件作为用于向被测太阳能电池发射具有不同波长的光的光源。 使用由相互正交的测试信号组成的一组测试信号数据为LED器件供电以发光。 太阳能电池在接收到由测试信号数据供电的LED装置的光时产生检测值，这些检测值又转换为电信号。 然后使用处理器装置来分离由各个LED装置贡献的分量信号与信号，并将分量信号与对应于测试信号数据的输出功率电平和/或从各个LED装置辐射的光能级进行比较， 从而获得太阳能电池对不同波长的光的光谱响应。

公开(公告)号：US20100271294A1

公开(公告)日：2010-10-28

申请号：US12563167

申请日：2009-09-21

Applicant: Chien-Yu Chen ,  Chen-Jung Chuang ,  Ming-Chieh Lin ,  Wen-Hsin Cheng

Inventor： Chien-Yu Chen ,  Chen-Jung Chuang ,  Ming-Chieh Lin ,  Wen-Hsin Cheng

IPC: G09G3/36

CPC classification number: G09G3/3655 ,  G09G2330/025 ,  G09G2330/06

Abstract: A method for reducing resonance energy of an LCD panel includes providing a plurality of driving signal patterns, each defining a non-overlap area width of a synchronization signal and a scan-line charging frequency, and determining an order of the plurality of driving signal patterns to modulate driving signals of the LCD panel accordingly.

Abstract translation: 一种用于降低LCD面板的共振能量的方法包括提供多个驱动信号图案，每个驱动信号图案限定同步信号和扫描线充电频率的非重叠区域宽度，并且确定多个驱动信号模式的顺序 以相应地调制LCD面板的驱动信号。

公开(公告)号：US20120287140A1

公开(公告)日：2012-11-15

申请号：US13420587

申请日：2012-03-14

Applicant: Ming-Chieh Lin ,  Ying-Yu Kuo ,  Wei-Ying Tu

Inventor： Ming-Chieh Lin ,  Ying-Yu Kuo ,  Wei-Ying Tu

IPC: G09G3/36 ,  G06F13/14

CPC classification number: G09G3/2096 ,  G09G2310/08 ,  G09G2320/0252 ,  G09G2360/127 ,  G09G2370/10

Abstract: A display interface circuit includes a physical layer circuit for receiving and modulating an original data signal and an original clock signal, a frame buffer for storing and outputting the data signal according to the clock signal and a command signal, a display serial interface for transmitting the data signal and the clock signal through packetization, a configuration register for generating the command signal according to an asynchronous clock signal and the data signal, and an asynchronous delay circuit for adjusting a clock latency that the clock signal takes to be sent to the configuration register to generate the asynchronous clock signal.

Abstract translation: 显示接口电路包括用于接收和调制原始数据信号和原始时钟信号的物理层电路，用于根据时钟信号和命令信号存储和输出数据信号的帧缓冲器，用于发送 数据信号和通过分组化的时钟信号，用于根据异步时钟信号和数据信号产生命令信号的配置寄存器，以及用于调整时钟信号需要发送到配置寄存器的时钟延迟的异步延迟电路 以产生异步时钟信号。

公开(公告)号：US20110096219A1

公开(公告)日：2011-04-28

申请号：US12795837

申请日：2010-06-08

Applicant: Pen-Jung Lee ,  Yu-Te Hsieh ,  Chiung-Kun Chuang ,  Ling-Ta Su ,  Ming-Chieh Lin

Inventor： Pen-Jung Lee ,  Yu-Te Hsieh ,  Chiung-Kun Chuang ,  Ling-Ta Su ,  Ming-Chieh Lin

IPC: H04N5/335 ,  H01L31/18

CPC classification number: H01L31/0203 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14683 ,  H01L31/02325 ,  H01L2224/45111 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2924/16235 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An image sensor package includes a substrate, an image sensor chip, a plurality of metal wires and an encapsulant. The substrate has an upper face, a lower face and a plurality of connecting pads arranged on the upper face. The image sensor chip has an active surface, a back surface opposite to the active surface and a plurality of bonding pads arranged on the active surface. The metal wires electrically connect the bonding pads of the image sensor chip to the connecting pads of the substrate. The transparent cover is arranged above the image sensor chip. A gap is formed between the transparent cover and the image sensor chip. The encapsulant is disposed around the transparent cover and the metal wires, and is used for sealing the metal wires and fixing the transparent cover above the image sensor chip.

Abstract translation: 图像传感器封装包括基板，图像传感器芯片，多个金属线和密封剂。 基板具有上表面，下表面和布置在上表面上的多个连接焊盘。 图像传感器芯片具有活性表面，与活性表面相对的后表面和布置在活性表面上的多个接合焊盘。 金属线将图像传感器芯片的接合焊盘电连接到衬底的连接焊盘。 透明盖布置在图像传感器芯片的上方。 在透明盖和图像传感器芯片之间形成间隙。 密封剂设置在透明盖和金属丝周围，用于密封金属线并将透明盖固定在图像传感器芯片上方。

公开(公告)号：US08321609B2

公开(公告)日：2012-11-27

申请号：US11612487

申请日：2006-12-19

Applicant: Ming-Chieh Lin ,  Hsieh-Yi Wu

Inventor： Ming-Chieh Lin ,  Hsieh-Yi Wu

IPC: G06F3/00

CPC classification number: G06F1/3203

Abstract: A power-saving control circuit and method suitable for circuits including a first-in-first-out (FIFO) register is provided. In the present invention, a logic circuit is disposed between two circuit modules with data transmitted in between. When there is data input into the FIFO register, the logic circuit activates a clock signal of the circuit module in the receiving end for reading the data. When all the data stored in the FIFO register is read, the clock signal is turned off so that the power consumed by the clock signal is reduced without affecting the data transmitting efficiency and the purpose of power-saving is achieved.

Abstract translation: 提供一种适用于包括先进先出（FIFO）寄存器的电路的省电控制电路和方法。 在本发明中，逻辑电路设置在两个电路模块之间，其间传输数据。 当数据输入FIFO寄存器时，逻辑电路激活接收端的电路模块的时钟信号，以读取数据。 当读取存储在FIFO寄存器中的所有数据时，时钟信号被关闭，从而在不影响数据传输效率的情况下降低时钟信号消耗的功率，从而达到省电的目的。

公开(公告)号：US20080126713A1

公开(公告)日：2008-05-29

申请号：US11612487

申请日：2006-12-19

Applicant: Ming-Chieh Lin ,  Hsieh-Yi Wu

Inventor： Ming-Chieh Lin ,  Hsieh-Yi Wu

IPC: G06F12/00

CPC classification number: G06F1/3203

Abstract: A power-saving control circuit and method suitable for circuits including a first-in-first-out (FIFO) register is provided. In the present invention, a logic circuit is disposed between two circuit modules with data transmitted in between. When there is data input into the FIFO register, the logic circuit activates a pulse signal of the circuit module in the receiving end for reading the data. When all the data stored in the FIFO register is read, the pulse signal is turned off so that the power consumed by the pulse signal is reduced without affecting the data transmitting efficiency and the purpose of power-saving is achieved.

Abstract translation: 提供一种适用于包括先进先出（FIFO）寄存器的电路的省电控制电路和方法。 在本发明中，逻辑电路设置在两个电路模块之间，其间传输数据。 当数据输入到FIFO寄存器中时，逻辑电路在接收端激活电路模块的脉冲信号，以读取数据。 当读取存储在FIFO寄存器中的所有数据时，脉冲信号被关闭，从而在不影响数据传输效率的情况下降低脉冲信号消耗的功率，从而达到省电的目的。

公开(公告)号：US20060228834A1

公开(公告)日：2006-10-12

申请号：US11102674

申请日：2005-04-11

Applicant: Pen-Jung Lee ,  Ling-Ta Su ,  Ming-Chieh Lin

Inventor： Pen-Jung Lee ,  Ling-Ta Su ,  Ming-Chieh Lin

IPC: H01L21/339

CPC classification number: H04N5/2253 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/1469 ,  H01L2924/0002 ,  H04N5/2257 ,  H01L2924/00

Abstract: A method of fabricating a CCDM scan module applied for image scan. A circuit board on which electronic devices are mounted is provided. A photo-detector and an integrated circuit device which is either packaged or unpackaged are also mounted on the circuit board to form an image sensor board. The electric connection between the photo-detector, the IC devices and the circuit board is established by wire-bonding technique. A module base is provided, and at least one reflection mirror and one transmission lens are mounted on the module base at predetermined positions. The image sensor board is then mounted on the module base at a position aligned with the lens for focusing an image.

Abstract translation: 一种应用于图像扫描的CCDM扫描模块的制造方法。 提供安装电子装置的电路板。 光电检测器和集成电路装置也被封装或未封装，也安装在电路板上以形成图像传感器板。 光电检测器，IC器件和电路板之间的电气连接通过引线键合技术建立。 提供模块底座，并且至少一个反射镜和一个透射透镜在预定位置安装在模块基座上。 然后，图像传感器板在与镜头对准的位置处安装在模块基座上，用于聚焦图像。

公开(公告)号：US20120229171A1

公开(公告)日：2012-09-13

申请号：US13412653

申请日：2012-03-06

Applicant: Liming Xiu ,  Ming-Chieh Lin

Inventor： Liming Xiu ,  Ming-Chieh Lin

IPC: H03B21/00

CPC classification number: G06F1/025 ,  G06F1/02 ,  G06F1/022 ,  G06F1/0328

Abstract: One of the advantages of direct frequency synthesis technique (e.g., flying-adder architecture) is its capability of generating arbitrary frequency by utilizing the time-average-frequency concept. In the clock output of the direct frequency synthesizer, instead of one type of cycle, there are two types of cycles. Unlike the conventional one-type-cycle clock wherein clock energy is concentrated at its designed frequency, Time-Average-Frequency based clock spreads some of its energy into spurious tones, which could be harmful to certain applications. The spurious tones are caused by the periodic carry sequence generated from a fractional part accumulator inside the frequency synthesizer. The invention suggests a method and an apparatus to break this periodicity and convert the spurious tones into broadband noise.

Abstract translation: 直接频率合成技术（例如飞行加法器结构）的优点之一是其通过利用时间平均频率概念产生任意频率的能力。 在直接频率合成器的时钟输出中，代替一种类型的周期，有两种类型的周期。 与其中时钟能量集中在其设计频率的常规单周期时钟不同，基于时间 - 平均频率的时钟将其一些能量扩展到伪噪声，这可能对某些应用有害。 伪噪声是由频率合成器内的分数分量累加器产生的周期性进位序列引起的。 本发明提出了一种破坏这种周期性并将伪噪声转换成宽带噪声的方法和装置。

公开(公告)号：US20120187999A1

公开(公告)日：2012-07-26

申请号：US13044566

申请日：2011-03-10

Applicant: Ming-Chieh Lin

Inventor： Ming-Chieh Lin

IPC: G06G7/12

CPC classification number: G06F7/544

Abstract: An interpolation circuit adapted to receive a plurality of inputs is provided. The inputs include a first input group and a second input group. The interpolation circuit includes a first selecting channel, a second selecting channel, and an interpolation unit. The first selecting channel receives the first input group and outputs a first input of the first input group according to a selecting signal. The second selecting channel receives the second input group and the first input and outputs a second input of the second input group according to the selecting signal. The first selecting channel and the second selecting channel respectively output the first input or the second input. The interpolation unit is coupled to the first selecting channel and the second selecting channel, and receives the first input and the second input, and accordingly performs an interpolation to output an interpolation result.

Abstract translation: 提供了适于接收多个输入的内插电路。 输入包括第一输入组和第二输入组。 插值电路包括第一选择信道，第二选择信道和插值单元。 第一选择通道接收第一输入组，并根据选择信号输出第一输入组的第一输入。 第二选择通道接收第二输入组和第一输入，并根据选择信号输出第二输入组的第二输入。 第一选择通道和第二选择通道分别输出第一输入或第二输入。 插值单元耦合到第一选择通道和第二选择通道，并且接收第一输入和第二输入，并且因此执行插值以输出插值结果。

公开(公告)号：US07678659B2

公开(公告)日：2010-03-16

申请号：US11421771

申请日：2006-06-02

Applicant: Chao-Chun Tu ,  Ming-Chieh Lin

Inventor： Chao-Chun Tu ,  Ming-Chieh Lin

IPC: H01L21/00

CPC classification number: H01L21/76816 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for reducing leakage current in a semiconductor capacitor. The method includes providing a top plate for collecting charge, providing a bottom plate for collecting an opposing charge to the top plate, providing a dielectric layer for insulation between the top plate and the bottom plate, providing a top contact, providing a bottom contact, providing a plurality of vias including top level vias for connecting the top plate to the top contact, and bottom level vias for connecting the bottom plate to the bottom contact; and separating a via and an adjacent structure such that their distance is greater than a minimum via spacing requirement of a foundry design rule for a semiconductor process producing the semiconductor capacitor.

Abstract translation: 一种用于减小半导体电容器中的漏电流的方法。 该方法包括提供用于收集电荷的顶板，提供用于收集与顶板相反的电荷的底板，提供用于在顶板和底板之间绝缘的介电层，提供顶部接触，提供底部接触， 提供多个通孔，包括用于将顶板连接到顶部触点的顶部通孔，以及用于将底板连接到底部触点的底部通孔; 以及分离通孔和相邻结构，使得它们的距离大于制造半导体电容器的半导体工艺的铸造设计规则的最小经过间隔要求。