Invention Grant
US08321609B2 Power-saving control circuit and method 失效
省电控制电路及方法

Power-saving control circuit and method
Abstract:
A power-saving control circuit and method suitable for circuits including a first-in-first-out (FIFO) register is provided. In the present invention, a logic circuit is disposed between two circuit modules with data transmitted in between. When there is data input into the FIFO register, the logic circuit activates a clock signal of the circuit module in the receiving end for reading the data. When all the data stored in the FIFO register is read, the clock signal is turned off so that the power consumed by the clock signal is reduced without affecting the data transmitting efficiency and the purpose of power-saving is achieved.
Public/Granted literature
Information query
Patent Agency Ranking
0/0