公开(公告)号：US09856582B2

公开(公告)日：2018-01-02

申请号：US13428395

申请日：2012-03-23

Applicant: Mina Ryo ,  Yoshiyuki Yonezawa ,  Takeshi Suzuki

Inventor： Mina Ryo ,  Yoshiyuki Yonezawa ,  Takeshi Suzuki

IPC: C30B17/00 ,  C30B29/36 ,  C30B9/10

CPC classification number: C30B29/36 ,  C30B9/10 ,  C30B17/00

Abstract: A method is disclosed with provides stable growth of SiC single crystals, particularly 4H—SiC single crystals, with an effective crystal growth rate for a prolonged time even at a low temperature range of 2000° C. or lower. A raw material containing Si, Ti and Ni is charged into a crucible made of graphite and heat-melted to obtain a solvent. At the same time, C is dissolved out from the crucible into the solvent to obtain a melt. A SiC seed crystal substrate is then brought into contact with the melt such that SiC is supersaturated in the melt in the vicinity of the surface of the SiC seed crystal substrate, thereby allowing growth and production of an SiC single crystal on the SiC seed crystal substrate.

公开(公告)号：US08178920B2

公开(公告)日：2012-05-15

申请号：US12574805

申请日：2009-10-07

Applicant: Shun-ichi Nakamura ,  Yoshiyuki Yonezawa

Inventor： Shun-ichi Nakamura ,  Yoshiyuki Yonezawa

IPC: H01L29/76

CPC classification number: H01L29/7813 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/7811

Abstract: A semiconductor device and a method of forming thereof has a base body has a field stopping layer, a drift layer, a current spreading layer, a body region, and a source contact region layered in the order on a substrate. A trench that reaches the field stopping layer or the substrate is provided. A gate electrode is provided in the upper half section in the trench. In a section deeper than the position of the gate electrode in the trench, an insulator is buried that has a normal value of insulation breakdown electric field strength equal to or greater than the value of the insulation breakdown electric field strength of the semiconductor material of the base body. This inhibits short circuit between a gate and a drain due to insulation breakdown of an insulator film at the bottom of the trench to realize a high breakdown voltage in a semiconductor device using a semiconductor material such as SiC. The sidewall surfaces of the trench located below the gate electrode is inclined to form a trapezoidal profile.

Abstract translation: 半导体器件及其形成方法具有在基板上依次层叠的场阻挡层，漂移层，电流扩展层，体区域和源极接触区域。 提供到达场停止层或基板的沟槽。 栅极电极设置在沟槽中的上半部分中。 在比沟槽中的栅电极的位置更深的部分中，埋入绝缘体的绝缘击穿电场强度的正常值等于或大于绝缘击穿电场强度的绝缘击穿电场强度 基体 由于沟槽底部的绝缘体膜的绝缘击穿，这就抑制了栅极和漏极之间的短路，从而在使用诸如SiC的半导体材料的半导体器件中实现高的击穿电压。 位于栅电极下方的沟槽的侧壁表面倾斜以形成梯形轮廓。

公开(公告)号：US5587793A

公开(公告)日：1996-12-24

申请号：US470157

申请日：1995-06-06

Applicant: Sadao Nakai ,  Yasukazu Izawa ,  Masanobu Yamanaka ,  Masato Ohmi ,  Masanori Akatsuka ,  Chiyoe Yamanaka ,  Yoshiyuki Yonezawa

Inventor： Sadao Nakai ,  Yasukazu Izawa ,  Masanobu Yamanaka ,  Masato Ohmi ,  Masanori Akatsuka ,  Chiyoe Yamanaka ,  Yoshiyuki Yonezawa

IPC: G01J4/04 ,  G01N21/23 ,  H01S3/00 ,  H01S3/05 ,  H01S3/08

CPC classification number: G01N21/23 ,  H01S3/08072

Abstract: A sample is placed between a circular polarizer and an analyzer in an optical path between a monochromatic light source and a two-dimensional optical receiver. Parallel beams emitted from the monochromatic light source are converted into circularly polarized light by the circular polarizer. After transmitting the sample, the light is guided to the analyzer. While rotating the analyzer about the axis of the beams, image data are detected by optical receiver at a step of a regular rotation angle, and the detected image data are sampled to be sent to an image processing device in the next stage. On the basis of the image data, an operation is conducted on each pixel to obtain a relative phase difference due to birefringence of the sample, the two-dimensional birefringence distribution including the sign of the relative phase difference, and also the principal axis direction.

Abstract translation: 将样品放置在单色光源和二维光接收器之间的光路中的圆偏振器和分析器之间。 从单色光源发射的平行光束通过圆偏振器转换为圆偏振光。 发送样品后，将光引导至分析仪。 在围绕光束的轴线旋转分析器的同时，以规则的旋转角度的步骤，通过光学接收器检测图像数据，并且对所检测的图像数据进行采样以在下一阶段中发送到图像处理装置。 基于图像数据，对每个像素执行操作以获得由于样品的双折射，包括相对相位差的符号的二维双折射分布以及主轴方向的相对相位差。

公开(公告)号：US09041006B2

公开(公告)日：2015-05-26

申请号：US12409964

申请日：2009-03-24

Applicant: Shun-ichi Nakamura ,  Yoshiyuki Yonezawa ,  Masahide Gotoh

Inventor： Shun-ichi Nakamura ,  Yoshiyuki Yonezawa ,  Masahide Gotoh

IPC: H01L29/15 ,  H01L29/66 ,  H01L21/04 ,  H01L29/08 ,  H01L29/78 ,  H01L29/861 ,  H01L29/06 ,  H01L29/16 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L21/046 ,  H01L29/0623 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/8613

Abstract: A silicon carbide MOS semiconductor device is disclosed which suppresses degradation of efficiency percentage yield with respect to a breakdown voltage even when a surface region with a high impurity concentration is formed by ion implantation with such a high dose as required for attaining a good ohmic contact. The device has a silicon carbide semiconductor substrate, a voltage blocking layer of a first conductivity type formed on the substrate, a body region of a second conductivity type formed on the voltage blocking layer, a body contact region of the second conductivity type formed in a surface region of the body region by selective ion implantation, a surface of the body contact region having such a high impurity concentration as to impart an ohmic contact, a source contact region of the first conductivity type formed in a surface region of the body region by selective ion implantation, a surface of the source contact region having such a high impurity concentration as to impart an ohmic contact, and a source extension region with an impurity concentration lower than that in the source contact region under the source contact region at a region deeper than a tail part of a bottom region of the source contact region by selective ion implantation, the source extension region having an impurity concentration less than 3×1019 cm−3.

Abstract translation: 公开了一种碳化硅MOS半导体器件，其即使当通过以达到良好的欧姆接触所需的高剂量的离子注入形成具有高杂质浓度的表面区域时，也可以相对于击穿电压降低效率百分比。 该器件具有碳化硅半导体衬底，形成在衬底上的第一导电类型的电压阻挡层，形成在电压阻挡层上的第二导电类型的体区，形成在第二导电类型的体接触区 通过选择性离子注入，体区域的表面区域，具有如此高的杂质浓度以产生欧姆接触的体接触区域的表面，在身体区域的表面区域中形成的第一导电类型的源极接触区域由 选择性离子注入，源极接触区域的表面具有如此高的杂质浓度以施加欧姆接触，以及源极延伸区域，其源极延伸区域的杂质浓度低于在源极接触区域下的源极接触区域中的杂质浓度 比源极接触区域的底部区域的尾部通过选择性离子注入，源极延伸区域具有杂质 浓度小于3×1019 cm-3。

公开(公告)号：US08324631B2

公开(公告)日：2012-12-04

申请号：US11865851

申请日：2007-10-02

Applicant: Yoshiyuki Yonezawa ,  Takeshi Tawara

Inventor： Yoshiyuki Yonezawa ,  Takeshi Tawara

IPC: H01L29/15 ,  H01L21/18

CPC classification number: H01L21/02579 ,  H01L21/02378 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/0262 ,  H01L29/66068

Abstract: A SiC semiconductor substrate is disclosed which includes a SiC single crystal substrate, a nitrogen (N)-doped n-type SiC epitaxial layer in which nitrogen (N) is doped and a phosphorus (P)-doped n-type SiC epitaxial layer in which phosphorus (P) is doped. The nitrogen (N)-doped n-type SiC epitaxial layer and the phosphorus (P)-doped n-type SiC epitaxial layer are laminated on the silicon carbide single crystal substrate sequentially. The nitrogen (N)-doped n-type SiC epitaxial layer and the phosphorus (P)-doped n-type SiC epitaxial layer are formed by using two or more different dopants, for example, nitrogen and phosphorus, at the time of epitaxial growth. Basal plane dislocations in a SiC device can be reduced.

Abstract translation: 公开了一种SiC半导体衬底，其包括SiC单晶衬底，氮（N）掺杂的n型SiC外延层，其中掺杂氮（N）和磷（P）掺杂的n型SiC外延层， 掺杂了磷（P）。 氮（N）掺杂的n型SiC外延层和磷（P）掺杂的n型SiC外延层依次层压在碳化硅单晶衬底上。 氮（N）掺杂的n型SiC外延层和磷（P）掺杂的n型SiC外延层通过在外延生长时使用两种或更多种不同的掺杂剂，例如氮和磷形成 。 可以减少SiC器件中的基面位错。

公开(公告)号：US20090236612A1

公开(公告)日：2009-09-24

申请号：US12409964

申请日：2009-03-24

Applicant: Shun-ichi Nakamura ,  Yoshiyuki Yonezawa ,  Masahide Gotoh

Inventor： Shun-ichi Nakamura ,  Yoshiyuki Yonezawa ,  Masahide Gotoh

IPC: H01L29/161

CPC classification number: H01L29/7813 ,  H01L21/046 ,  H01L29/0623 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/8613

Abstract: A silicon carbide MOS semiconductor device is disclosed which suppresses degradation of efficiency percentage yield with respect to a breakdown voltage even when a surface region with a high impurity concentration is formed by ion implantation with such a high dose as required for attaining a good ohmic contact. The device has a silicon carbide semiconductor substrate, a voltage blocking layer of a first conductivity type formed on the substrate, a body region of a second conductivity type formed on the voltage blocking layer, a body contact region of the second conductivity type formed in a surface region of the body region by selective ion implantation, a surface of the body contact region having such a high impurity concentration as to impart an ohmic contact, a source contact region of the first conductivity type formed in a surface region of the body region by selective ion implantation, a surface of the source contact region having such a high impurity concentration as to impart an ohmic contact, and a source extension region with an impurity concentration lower than that in the source contact region under the source contact region at a region deeper than a tail part of a bottom region of the source contact region by selective ion implantation, the source extension region having an impurity concentration less than 3×1019 cm−3.

Abstract translation: 公开了一种碳化硅MOS半导体器件，其即使当通过以达到良好的欧姆接触所需的高剂量的离子注入形成具有高杂质浓度的表面区域时，也可以相对于击穿电压降低效率百分比。 该器件具有碳化硅半导体衬底，形成在衬底上的第一导电类型的电压阻挡层，形成在电压阻挡层上的第二导电类型的体区，形成在第二导电类型的体接触区 通过选择性离子注入，体区域的表面区域，具有如此高的杂质浓度以产生欧姆接触的体接触区域的表面，在身体区域的表面区域中形成的第一导电类型的源极接触区域由 选择性离子注入，源极接触区域的表面具有如此高的杂质浓度以施加欧姆接触，以及源极延伸区域，其源极延伸区域的杂质浓度低于在源极接触区域下的源极接触区域中的杂质浓度 比源极接触区域的底部区域的尾部通过选择性离子注入，源极延伸区域具有杂质 浓度小于3×1019 cm-3。

公开(公告)号：US06888156B2

公开(公告)日：2005-05-03

申请号：US10179006

申请日：2002-06-26

Applicant: Toyohiro Chikyow ,  Hideomi Koinuma ,  Masashi Kawasaki ,  Yoo Young Zo ,  Yoshinori Konishi ,  Yoshiyuki Yonezawa

Inventor： Toyohiro Chikyow ,  Hideomi Koinuma ,  Masashi Kawasaki ,  Yoo Young Zo ,  Yoshinori Konishi ,  Yoshiyuki Yonezawa

IPC: H01L21/20 ,  H01L21/36 ,  H01L29/06 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L21/0328

CPC classification number: H01L21/02381 ,  H01L21/02472 ,  H01L21/02474 ,  H01L21/02491 ,  H01L21/0254

Abstract: The invention provides a thin film device where ionic crystals are epitaxially grown on a Si single crystal substrate through a proper buffer layer, and its for fabrication method. A ZnS layer is first deposited on a Si single crystal substrate. Ionic crystal thin films (an n-GaN layer, a GaN layer, and a p-GaN layer) are deposited thereon. The ZnS thin film is an oriented film excellent in crystallinity and has excellent surface flatness. When ZnS can be once epitaxially grown on the Si single crystal substrate, the ionic crystal thin films can be easily epitaxially grown subsequently. Therefore, ZnS is formed to be a buffer layer, whereby even ionic crystals having differences in lattice constants from Si can be easily epitaxially grown in an epitaxial thin film with few lattice defects on the Si single crystal substrate. The characteristics of a thin film device utilizing it can be enhanced.

Abstract translation: 本发明提供了一种薄膜器件，其中通过适当的缓冲层在Si单晶衬底上外延生长离子晶体及其制造方法。 首先将ZnS层沉积在Si单晶衬底上。 在其上沉积离子晶体薄膜（n-GaN层，GaN层和p-GaN层）。 ZnS薄膜是结晶性优异且表面平坦性优异的取向膜。 当ZnS可以在Si单晶衬底上一次外延生长时，离子晶体薄膜随后可以容易地外延生长。 因此，ZnS形成为缓冲层，由此，即使在Si单晶衬底上具有很少晶格缺陷的外延薄膜中也可以容易地外延生长与Si的晶格常数不同的离子晶体。 可以提高利用它的薄膜器件的特性。

公开(公告)号：US20100314247A1

公开(公告)日：2010-12-16

申请号：US12662832

申请日：2010-05-05

Applicant: Shinya Takashima ,  Masanori Ooto ,  Yoshiyuki Yonezawa

Inventor： Shinya Takashima ,  Masanori Ooto ,  Yoshiyuki Yonezawa

IPC: C23C14/35

CPC classification number: C23C14/325 ,  C23C14/0605 ,  H01J37/32055 ,  H01J37/32357

Abstract: A filtered cathodic arc device includes a plasma generating module which generates plasma using an arc discharge which has a cathode target as a deposition raw material; a deposition processing chamber in which a deposition receiving substrate is placed; a curved magnetic field duct that is placed between the plasma generating module and the deposition processing chamber, and that guides plasma generated by the plasma generating module to the deposition processing chamber with a magnetic field; a wool medium formed of a nonmagnetic metal fiber which covers the interior wall of the magnetic field duct; and a bias power source for the wool medium. The device balances reduction of particulate particles and a high deposition rate.

Abstract translation: 一种过滤的阴极电弧装置包括：等离子体产生模块，其使用具有阴极靶作为沉积原料的电弧放电产生等离子体; 沉积处理室，其中放置有沉积接收基板; 放置在等离子体发生模块和沉积处理室之间的弯曲的磁场导管，其将由等离子体产生模块产生的等离子体引导到具有磁场的沉积处理室; 由覆盖磁场导管内壁的非磁性金属纤维形成的羊毛介质; 和羊毛介质的偏置电源。 该装置平衡颗粒颗粒的还原和高沉积速率。

公开(公告)号：US07821014B2

公开(公告)日：2010-10-26

申请号：US11683993

申请日：2007-03-08

Applicant: Yoshiyuki Yonezawa ,  Daisuke Kishimoto

Inventor： Yoshiyuki Yonezawa ,  Daisuke Kishimoto

IPC: H01L31/0312 ,  H01L29/06 ,  H01L21/332 ,  H01L21/8222

CPC classification number: H01L29/66068 ,  H01L21/0465 ,  H01L29/7827

Abstract: A semiconductor device and a manufacturing method thereof uses a semiconductor substrate of silicon carbide. On one principal surface side of the substrate, at its central section, a layer of silicon carbide or gallium nitride as a semiconductor layer having the thickness at least necessary for breakdown voltage blocking is epitaxially grown or formed from part of the substrate. A recess is formed in the other principal surface side of substrate at a position facing the central section. A supporting section surrounds the bottom of the recess and provides the side face of the recess. The recess is formed by processing such as dry etching. The semiconductor device, even though the semiconductor substrate is made thinner for the realization of small on-resistance, can maintain the strength of the semiconductor substrate capable of reducing occurrence of a wafer cracking during the manufacturing process.

Abstract translation: 半导体器件及其制造方法使用碳化硅的半导体衬底。 在衬底的一个主表面上，在其中心部分，由衬底的一部分外延生长或形成具有至少为击穿电压阻挡所必需的厚度的半导体层的碳化硅或氮化镓层。 在面向中心部的位置的基板的另一主面侧形成有凹部。 支撑部分围绕凹部的底部并且提供凹部的侧面。 凹部通过诸如干法蚀刻的处理形成。 半导体器件即使半导体衬底被制成较薄以实现小的导通电阻，也可以在制造过程中保持能够减少晶片开裂发生的半导体衬底的强度。

公开(公告)号：US07615849B2

公开(公告)日：2009-11-10

申请号：US11530850

申请日：2006-09-11

Applicant: Shun-Ichi Nakamura ,  Yoshiyuki Yonezawa ,  Hiroyuki Fujisawa ,  Takashi Tsuji

Inventor： Shun-Ichi Nakamura ,  Yoshiyuki Yonezawa ,  Hiroyuki Fujisawa ,  Takashi Tsuji

IPC: H01L29/04 ,  H01L29/06

CPC classification number: H01L29/7813 ,  H01L21/046 ,  H01L29/045 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  Y10S438/931

Abstract: In a semiconductor device having SiC vertical trench MOSFETs, it is aimed to prevent the generation of large scattering in the channel resistance without largely increasing the average value of channel resistance. A 4H-SiC substrate having a major face thereof that is generally a {0001} face and having an off angle α. The trench is formed with the standard deviation σ in scattering of the angle formed by a trench side wall face and a substrate major face within a wafer face. By setting the designed value of the angle formed by the trench side wall face and the substrate major face at an any angle ranging from [(60 degrees)+2σ] to [(90 degrees)−tan−1 (0.87×tan α)−2σ] in forming the trench in the SiC substrate, a semiconductor device in which the angle formed by the trench side wall face and the substrate major face is 60 degrees or more but not more than [(90 degrees)−tan−1 (0.87×tan α)] can be obtained.

Abstract translation: 在具有SiC垂直沟槽MOSFET的半导体器件中，旨在防止在沟道电阻中产生大的散射，而不会大大增加沟道电阻的平均值。 具有主面的4H-SiC衬底通常为{0001}面并具有偏角α。 沟槽由晶片面内的沟槽侧壁面和基板主面所形成的角度的散射形成有标准偏差σ。 通过将沟槽侧壁面和基板主面形成的角度的设计值设定为从[（60度）+2σ]到[（90度）-an-1（0.87葡萄糖α） - 在SiC衬底中形成沟槽的半导体器件，其中由沟槽侧壁面和衬底主面形成的角度为60度以上但不大于[（90度）-an -1（0.87） xtan alpha）]。