公开(公告)号：US11901005B2

公开(公告)日：2024-02-13

申请号：US16953092

申请日：2020-11-19

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Michael A. Shore

IPC: G11C11/00 ,  G11C14/00 ,  G11C11/22 ,  G11C11/4091 ,  G11C11/4097 ,  H01L49/02 ,  G11C11/4096 ,  H01L27/105 ,  H10B12/00 ,  H10B53/30 ,  H10B53/40

CPC classification number: G11C14/0027 ,  G11C11/005 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  H01L27/105 ,  H01L28/40 ,  H01L28/55 ,  H10B12/00 ,  H10B12/09 ,  H10B12/30 ,  H10B53/30 ,  H10B53/40

Abstract: Apparatuses and methods for memory including ferroelectric memory cells and dielectric memory cells are disclosed. The apparatus includes a first memory cell including first and second ferroelectric capacitors configured to store charges representing complementary logical values, a second memory cell including first and second dielectric capacitors configured to store charges representing complementary logical values, a first bit line selectably coupled to the first ferroelectric capacitor of the first memory cell and to the first dielectric capacitor of the second memory cell, a second bit line selectably coupled to the second ferroelectric capacitor of the first memory cell and to the second dielectric capacitor of the second memory cell, and a sense amplifier coupled to the first and second bit lines.

公开(公告)号：US11636890B2

公开(公告)日：2023-04-25

申请号：US17370515

申请日：2021-07-08

Applicant: Micron Technology, Inc.

Inventor： Charles L. Ingalls ,  Scott J. Derner

IPC: G11C11/00 ,  G11C11/22

Abstract: Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic state of the cell. That is, the actual logic state of one or more memory cells may be inverted, but the intended logic state of the memory cells may remain unchanged. Different sets of transistors may be configured around a sense component of a cell to enable reading and writing of intended and inverted logic states from or to the cell. For instance, a first set of transistors may be used to read the logic state currently stored at a memory cell, while a second set of transistors may be used to read a logic state inverted from the currently stored logic state.

公开(公告)号：US11227861B2

公开(公告)日：2022-01-18

申请号：US17125651

申请日：2020-12-17

Applicant: Micron Technology, Inc.

Inventor： Hiroki Fujisawa ,  Charles L. Ingalls ,  Richard J. Hill ,  Gurtej S. Sandhu ,  Scott J. Derner

IPC: G11C11/40 ,  H01L25/18 ,  G11C11/4091 ,  H01L23/528 ,  H01L27/108 ,  G11C11/408 ,  H01L29/78

Abstract: Some embodiments include an integrated assembly having a base comprising sense-amplifier-circuitry, a first deck over the base, and a second deck over the first deck. The first deck includes a first portion of a first array of first memory cells, and includes a first portion of a second array of second memory cells. The second deck includes a second portion of the first array of the first memory cells, and includes a second portion of the second array of the second memory cells. A first digit line is associated with the first array, and a second digit line is associated with the second array. The first and second digit lines are comparatively coupled with one another through the sense-amplifier-circuitry.

公开(公告)号：US11222975B2

公开(公告)日：2022-01-11

申请号：US16522390

申请日：2019-07-25

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Steve V. Cole ,  Scott J. Derner ,  Toby D. Robbs

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/108 ,  H01L27/11587 ,  G11C11/22 ,  G11C11/4091

Abstract: An apparatus, such as a memory array, can have a memory cell coupled to a first digit line (e.g., a local digit line) at a first level. A second digit line (e.g., hierarchical digit line) at a second level can be coupled to a main sense amplifier. A charge sharing device at a third level between the first and second levels can be coupled to the first digit line and to a connector. A vertical transistor at the third level can be coupled between the first digit line and the connector. A contact can be coupled between the connector and the second digit line.

公开(公告)号：US11145358B2

公开(公告)日：2021-10-12

申请号：US16543315

申请日：2019-08-16

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner

IPC: G11C7/12 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4094 ,  G11C7/06 ,  G11C8/08 ,  G11C11/4099 ,  G11C7/14

Abstract: An apparatus includes a sense amplifier, a plurality of storage memory cells coupled to the sense amplifier via a first digit line, and a plurality of offset memory cells coupled to the sense amplifier via a second digit line. The plurality of storage memory cells and the plurality of offset memory cells can comprise an array of memory cells. Each of the storage memory cells and the offset memory cells can include a respective capacitor having a particular capacitance.

公开(公告)号：US20210272958A1

公开(公告)日：2021-09-02

申请号：US17324976

申请日：2021-05-19

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: H01L27/108 ,  H01L29/78 ,  G11C11/4094 ,  G11C11/4091

Abstract: Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.

公开(公告)号：US20210249416A1

公开(公告)日：2021-08-12

申请号：US16785942

申请日：2020-02-10

Applicant: Micron Technology, Inc.

Inventor： Jiyun Li ,  Scott J. Derner

IPC: H01L27/108 ,  H01L23/522 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/408

Abstract: Some embodiments include an integrated assembly having first conductive lines which extend along a first direction, and having second conductive lines over the first conductive lines and which extend along a second direction that crosses the first direction. Capacitors are over the second conductive lines. The second conductive lines are operatively proximate active structures to gatedly couple a first set of the capacitors to the first conductive lines through the active structures. Shield structures are between the first conductive lines and extend along the first direction. A voltage source is electrically coupled to the shield structures through a second set of the capacitors. Some embodiments include assemblies having two or more decks stacked one atop another.

公开(公告)号：US11069385B1

公开(公告)日：2021-07-20

申请号：US16835797

申请日：2020-03-31

Applicant: Micron Technology, inc.

Inventor： Jiyun Li ,  Scott J. Derner

IPC: G11C11/24 ,  G11C7/08 ,  G11C11/4091 ,  H01L27/108

Abstract: Some embodiments include an integrated assembly having a second deck over a first deck. A first true digit line has first and second segments along the first deck. A first complementary digit line has third and fourth segments along the second deck. The first true digit line is comparatively compared to the first complementary digit line. A second true digit line has a third region along the first deck and a fourth region along the second deck. The third region is adjacent the first segment, and the fourth region is adjacent the third segment. A second complementary digit line has a fifth region along the first deck and has a sixth region along the second deck. The fifth region is adjacent the second segment, and the sixth region is adjacent the fourth segment. The second true digit line is comparatively compared to the second complementary digit line.

公开(公告)号：US20210074714A1

公开(公告)日：2021-03-11

申请号：US17083208

申请日：2020-10-28

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: H01L27/11507 ,  H01L23/528 ,  H01L27/108 ,  H01L27/11514 ,  H01L29/78 ,  H01L29/08

Abstract: Some embodiments include an integrated assembly. The integrated assembly has a first transistor with a horizontally-extending channel region between a first source/drain region and a second source/drain region; has a second transistor with a vertically-extending channel region between a third source/drain region and a fourth source/drain region; and has a capacitor between the first and second transistors. The capacitor has a first electrode, a second electrode, and an insulative material between the first and second electrodes. The first electrode is electrically connected with the first source/drain region, and the second electrode is electrically connected with the third source/drain region. A digit line is electrically connected with the second source/drain region. A conductive structure is electrically connected with the fourth source/drain region.

公开(公告)号：US20210028176A1

公开(公告)日：2021-01-28

申请号：US16522336

申请日：2019-07-25

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: H01L27/108 ,  H01L29/786 ,  H01L23/528 ,  G11C11/4091 ,  H01L27/02

Abstract: An apparatus can have first and second memory cells. The first memory cell can have a first storage device selectively coupled to a first digit line at a first level by a first vertical transistor at a second level. The second memory cell can have a second storage device selectively coupled to a second digit line at the first level by a second vertical transistor at the second level. A third digit line can be at a third level and can be coupled to a main sense amplifier. A local sense amplifier can be coupled to the first digit line, the second digit line, and the third digit line. The second level can be between the first and third levels.