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    Multi-decks memory device including inter-deck switches
    1.
    发明授权
    Multi-decks memory device including inter-deck switches 有权

    公开(公告)号：US10475515B2

    公开(公告)日：2019-11-12

    申请号：US15850708

    申请日：2017-12-21

    Applicant: Micron Technology, Inc.

    Inventor： Benben Li ,  Akira Goda ,  Ramey M. Abdelrahaman ,  Ian C. Laboriante ,  Krishna K. Parat

    IPC: G11C16/04 ,  H01L27/11524 ,  H01L45/00 ,  H01L27/24 ,  H01L27/11597 ,  H01L27/11558 ,  G11C11/408 ,  G11C8/08

    Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

    Multi-decks memory device including inter-deck switches
    2.
    发明授权
    Multi-decks memory device including inter-deck switches 有权

    公开(公告)号：US11289163B2

    公开(公告)日：2022-03-29

    申请号：US17087166

    申请日：2020-11-02

    Applicant: Micron Technology, Inc.

    Inventor： Benben Li ,  Akira Goda ,  Ramey M. Abdelrahaman ,  Ian C. Laboriante ,  Krishna K. Parat

    IPC: G11C16/04 ,  H01L27/11558 ,  H01L27/11524 ,  H01L45/00 ,  G11C11/408 ,  H01L27/24 ,  H01L27/11597 ,  G11C8/08 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157

    Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

    MULTI-DECKS MEMORY DEVICE INCLUDING INTER-DECK SWITCHES
    3.
    发明申请
    MULTI-DECKS MEMORY DEVICE INCLUDING INTER-DECK SWITCHES 有权

    公开(公告)号：US20220284959A1

    公开(公告)日：2022-09-08

    申请号：US17706087

    申请日：2022-03-28

    Applicant: Micron Technology, Inc.

    Inventor： Benben Li ,  Akira Goda ,  Ramey M. Abdelrahaman ,  Ian C. Laboriante ,  Krishna K. Parat

    IPC: G11C16/04 ,  H01L27/11558 ,  H01L27/11524 ,  H01L45/00 ,  G11C11/408 ,  H01L27/24 ,  H01L27/11597 ,  G11C8/08 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157

    Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

    Multi-decks memory device including inter-deck switches
    4.
    发明授权
    Multi-decks memory device including inter-deck switches 有权

    公开(公告)号：US10825523B2

    公开(公告)日：2020-11-03

    申请号：US16667465

    申请日：2019-10-29

    Applicant: Micron Technology, Inc.

    Inventor： Benben Li ,  Akira Goda ,  Ramey M. Abdelrahaman ,  Ian C. Laboriante ,  Krishna K. Parat

    IPC: G11C16/04 ,  H01L27/11558 ,  H01L27/11524 ,  H01L45/00 ,  G11C11/408 ,  H01L27/24 ,  H01L27/11597 ,  G11C8/08 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157

    Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

    Methods of forming a programmable region that comprises a multivalent metal oxide portion and an oxygen containing dielectric portion
    7.
    发明授权
    Methods of forming a programmable region that comprises a multivalent metal oxide portion and an oxygen containing dielectric portion 有权
    形成包括多价金属氧化物部分和含氧电介质部分的可编程区域的方法

    公开(公告)号：US08809157B2

    公开(公告)日：2014-08-19

    申请号：US14105623

    申请日：2013-12-13

    Applicant: Micron Technology, Inc.

    Inventor： D. V. Nirmal Ramaswamy ,  Beth R. Cook ,  Lei Bi ,  Wayne Huang ,  Ian C. Laboriante

    IPC: H01L21/20

    CPC classification number: H01L45/1608 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

    Abstract: A method of forming a memory cell includes forming one of multivalent metal oxide material or oxygen-containing dielectric material over a first conductive structure. An outer surface of the multivalent metal oxide material or the oxygen-containing dielectric material is treated with an organic base. The other of the multivalent metal oxide material or oxygen-containing dielectric material is formed over the treated outer surface. A second conductive structure is formed over the other of the multivalent metal oxide material or oxygen-containing dielectric material.

    Abstract translation: 形成存储单元的方法包括在第一导电结构上形成多价金属氧化物材料或含氧电介质材料之一。 用有机碱处理多价金属氧化物材料或含氧电介质材料的外表面。 另外的多价金属氧化物材料或含氧电介质材料形成在经处理的外表面上。 在多价金属氧化物材料或含氧介电材料的另一个上形成第二导电结构。

    MULTI-DECKS MEMORY DEVICE INCLUDING INTER-DECK SWITCHES
    9.
    发明申请
    MULTI-DECKS MEMORY DEVICE INCLUDING INTER-DECK SWITCHES 有权

    公开(公告)号：US20210118508A1

    公开(公告)日：2021-04-22

    申请号：US17087166

    申请日：2020-11-02

    Applicant: Micron Technology, Inc.

    Inventor： Benben Li ,  Akira Goda ,  Ramey M. Abdelrahaman ,  Ian C. Laboriante ,  Krishna K. Parat

    IPC: G11C16/04 ,  H01L27/11558 ,  H01L27/11524 ,  H01L45/00 ,  G11C11/408 ,  H01L27/24 ,  H01L27/11597 ,  G11C8/08 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157

    Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

    MULTI-DECKS MEMORY DEVICE INCLUDING INTER-DECK SWITCHES
    10.
    发明申请
    MULTI-DECKS MEMORY DEVICE INCLUDING INTER-DECK SWITCHES 审中-公开

    公开(公告)号：US20200066346A1

    公开(公告)日：2020-02-27

    申请号：US16667465

    申请日：2019-10-29

    Applicant: Micron Technology, Inc.

    Inventor： Benben Li ,  Akira Goda ,  Ramey M. Abdelrahaman ,  Ian C. Laboriante ,  Krishna K. Parat

    IPC: G11C16/04 ,  H01L27/11558 ,  H01L27/11524 ,  H01L45/00 ,  G11C11/408 ,  H01L27/24 ,  H01L27/11597 ,  G11C8/08 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157

    Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

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