公开(公告)号：US11721404B2

公开(公告)日：2023-08-08

申请号：US17484777

申请日：2021-09-24

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Preston A. Thomson ,  Michael G. Miller ,  Gary F. Besinga ,  Scott A. Stoller ,  Sampath K. Ratnam ,  Renato C. Padilla ,  Peter Feeley

IPC: G11C16/30 ,  G11C16/34 ,  G11C16/12

CPC classification number: G11C16/349 ,  G11C16/12 ,  G11C2211/5641

Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.

公开(公告)号：US11715541B2

公开(公告)日：2023-08-01

申请号：US17867538

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Renato C. Padilla ,  Sampath K. Ratnam ,  Christopher M. Smitchger ,  Vamsi Pavan Rayaprolu ,  Gary F. Besinga ,  Michael G. Miller ,  Tawalin Opastrakoon

IPC: G11C29/10 ,  G06F11/07 ,  G11C29/52 ,  G06F11/10

CPC classification number: G11C29/10 ,  G06F11/076 ,  G06F11/0736 ,  G06F11/0757 ,  G06F11/1048 ,  G11C29/52

Abstract: A method includes associating each block of a plurality of blocks of a memory device with a corresponding frequency access group of a plurality of frequency access groups based on corresponding access frequencies, and performing scan operations on blocks of each of the plurality of frequency access groups using a scan frequency that is different from scan frequencies of other frequency access groups. A scan operation performed on a frequency access group with a higher access frequency uses a higher scan frequency than a scan operation performed on a frequency access group with a lower access frequency.

公开(公告)号：US11456051B1

公开(公告)日：2022-09-27

申请号：US17212531

申请日：2021-03-25

Applicant: Micron Technology, Inc.

Inventor： Gary F. Besinga ,  Renato C. Padilla ,  Tawalin Opastrakoon ,  Sampath K. Ratnam ,  Michael G. Miller ,  Christopher M. Smitchger ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe

IPC: G11C29/44 ,  G11C29/42 ,  G11C16/26 ,  G11C29/00 ,  G11C16/10 ,  G11C29/50

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving a set of read offsets for a block of the memory device, the set of read offsets comprising a default read offset, selecting the default read offset from the set of read offsets based on one or more criteria, applying the default read offset to a read operation performed with respect to the block, determining that a second set of criteria associated with removing the default read offset is satisfied, and removing the default read offset responsive to determining that the second set of criteria is satisfied.

公开(公告)号：US20220199179A1

公开(公告)日：2022-06-23

申请号：US17127012

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Renato C. Padilla ,  Sampath K. Ratnam ,  Christopher M. Smitchger ,  Vamsi Pavan Rayaprolu ,  Gary F. Besinga ,  Michael G. Miller ,  Tawalin Opastrakoon

IPC: G11C29/10

Abstract: In one embodiment, a system maintains metadata associating each block of a plurality of blocks of the memory device with a corresponding frequency access group, where each frequency access group is associated with a corresponding scan frequency. The system determines that a first predetermined time period has elapsed since a last scan operation performed with respect to one or more blocks of the memory device, where the first predetermined time period specifies a first scan frequency. The system selects, based on the metadata, at least one block from a first frequency access group associated with the first scan frequency. The system performs a scan operation with respect to the selected block.

公开(公告)号：US20220066650A1

公开(公告)日：2022-03-03

申请号：US17007539

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Gary F. Besinga

IPC: G06F3/06

Abstract: An asynchronous power loss (APL) event is detected at a memory device. A last written page is identified in the memory device in response to detecting the APL event. A count of zeros programmed in the last written page is determined. The count of zeros is compared to a threshold constraint to determine whether to perform a dummy write operation on the last written page.

公开(公告)号：US20200160894A1

公开(公告)日：2020-05-21

申请号：US16749481

申请日：2020-01-22

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Harish Reddy Singidi ,  Gianni Stephen Alsasua ,  Gary F. Besinga ,  Sampath Ratnam ,  Peter Sean Feeley

IPC: G11C7/10 ,  G11C29/02 ,  G11C8/10

Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a read level calibration based on inputs from one or more trackers monitoring parameters associated with the memory device and a determination of an occurrence of at least one event from a set of events related to the monitored parameters. The monitored parameters can include parameters related to a selected time interval and measurements of read, erase, or write operations of the memory device. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US10579307B2

公开(公告)日：2020-03-03

申请号：US16566545

申请日：2019-09-10

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi ,  Sampath Ratnam ,  Renato Padilla, Jr. ,  Gary F. Besinga ,  Peter Sean Feeley

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/08

Abstract: Devices and techniques for correcting for power loss in NAND memory devices are disclosed herein. The NAND memory devices may comprise a number of physical pages. For example, a memory controller may detect a power loss indicator at the NAND flash memory. The memory controller may identify a last-written physical page and determine whether the last-written physical page comprises more than a threshold number of low-read-margin cells. If the last-written physical page comprises more than the threshold number of low-read-margin cells, the memory controller may provide a programming voltage to at least the low-read-margin cells.

公开(公告)号：US10366763B2

公开(公告)日：2019-07-30

申请号：US15799616

申请日：2017-10-31

Applicant: Micron Technology, Inc.

Inventor： Harish Singidi ,  Kishore Kumar Muchherla ,  Gianni Stephen Alsasua ,  Ashutosh Malshe ,  Sampath Ratnam ,  Gary F. Besinga ,  Michael G. Miller

IPC: G11C16/26 ,  G11C16/08

Abstract: Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.

公开(公告)号：US20180374549A1

公开(公告)日：2018-12-27

申请号：US15633377

申请日：2017-06-26

Applicant: Micron Technology, Inc.

Inventor： Renato C. Padilla ,  Jung Sheng Hoei ,  Michael G. Miller ,  Roland J. Awusie ,  Sampath K. Ratnam ,  Kishore Kumar Muchherla ,  Gary F. Besinga ,  Ashutosh Malshe ,  Harish R. Singidi

IPC: G11C16/34

CPC classification number: G11C16/3427 ,  G11C11/5642 ,  G11C16/3422 ,  G11C16/3431

Abstract: A memory device comprising a main memory and a controller operably connected to the main memory is provided. The main memory can comprise a plurality of memory addresses, each corresponding to a single one of a plurality of word lines. Each memory address can be included in a tracked subset of the plurality of memory addresses. Each tracked subset can include memory addresses corresponding to more than one of the plurality of word lines. The controller is configured to track a number of read operations for each tracked subset, and to scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset.

公开(公告)号：US09921898B1

公开(公告)日：2018-03-20

申请号：US15390833

申请日：2016-12-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael G. Miller ,  Ashutosh Malshe ,  Violante Moschiano ,  Peter Feeley ,  Gary F. Besinga ,  Sampath K. Ratnam ,  Walter Di-Francesco ,  Renato C. Padilla, Jr. ,  Yun Li ,  Kishore Kumar Muchherla

IPC: G11C16/04 ,  G06F11/07 ,  G06F3/06

CPC classification number: G06F11/073 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079

Abstract: Apparatus and methods of operating such apparatus include iteratively programming a group of memory cells to respective desired data states, wherein a particular memory cell is configured to store overhead data and a different memory cell is configured to store user data; determining whether a power loss to the apparatus is indicated while iteratively programming the group of memory cells; and if a power loss to the apparatus is indicated, changing the desired data state of the particular memory cell before continuing with the programming. Apparatus and methods of operating such apparatus further include reading a data state of a particular memory cell of a last written page of memory cells, and marking the page as affected by power loss during a programming operation if the particular memory cell has any data state other than a particular data state.