公开(公告)号：US20240411680A1

公开(公告)日：2024-12-12

申请号：US18330007

申请日：2023-06-06

Applicant: Mellanox Technologies, Ltd.

Inventor： Gil Kremer ,  Roee Moyal ,  Igor Voks ,  Liel Peled ,  Eliel Peretz ,  Ariel Shahar

IPC: G06F12/02

Abstract: Apparatuses, systems, and techniques for dynamic memory allocation using a shared free list. A user tag is received, and a hashed user tag is generated. A first reference to an entry in a second data structure is identified in a first data structure using the hashed user tag. The entry includes multiple user tags. Responsive to determining that the multiple user tags do not include the user tag, a memory address is identified in a third data structure. The memory address is removed from the third data structure. Memory is allocated for a user context associated with the user tag at the memory address. The user tag is added to the second data structure.

公开(公告)号：US20240345963A1

公开(公告)日：2024-10-17

申请号：US18299732

申请日：2023-04-13

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Gal Shalom ,  Daniel Marcovitch ,  Ran Avraham Koren ,  Amir Sharaffy ,  Shay Aisman ,  Ariel Shahar

IPC: G06F12/1027 ,  G06F12/0811 ,  G06F12/0891

CPC classification number: G06F12/1027 ,  G06F12/0811 ,  G06F12/0891 ,  G06F2212/1021

Abstract: A peripheral device includes a bus interface and an Address Translation Service (ATS) controller. The bus interface is to communicate over a peripheral bus. The ATS controller is to communicate over the peripheral bus, including sending address translation requests and receiving address translations in response to the address translation requests, to cache at least some of the address translations in one or more Address Translation Caches (ATCs), to estimate one or more statistical properties of the received address translations, and to configure the one or more ATCs based on the one or more statistical properties.

公开(公告)号：US20240311183A1

公开(公告)日：2024-09-19

申请号：US18479784

申请日：2023-10-02

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Ariel Shahar ,  Wojciech Wasko ,  Dotan David Levi ,  Roee Moyal ,  Eliel Peretz

IPC: G06F9/48 ,  G06F9/54

CPC classification number: G06F9/4881 ,  G06F9/542

Abstract: A work descriptor identifying a plurality of workflow tasks to be performed by a hardware device is generated by a host system. A plurality of timestamp logging tasks are added to the work descriptor. Each of the plurality of timestamp logging tasks corresponds to one of the plurality of workflow tasks and instructs the hardware device to log a timestamp in response to an event associated with a respective workflow task. The work descriptor with the plurality of timestamp logging tasks is stored in a work queue of the host system. The work queue is accessible by the hardware device.

公开(公告)号：US20240146664A1

公开(公告)日：2024-05-02

申请号：US17979018

申请日：2022-11-02

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Gal Yefet ,  Daniel Marcovitch ,  Roee Moyal ,  Gil Bloch ,  Ariel Shahar ,  Yossef Itigin

IPC: H04L47/625 ,  H04L47/62 ,  H04L47/6275

CPC classification number: H04L47/6255 ,  H04L47/6225 ,  H04L47/6275

Abstract: In one embodiment, a system includes a memory to store a work queue including work queue entry slots, a processing device to write work queue entries to the work queue in a consecutive and cyclic manner, and a network device including a network interface to share packet over a network, and packet processing circuitry to read the work queue entries from the work queue in a consecutive and cyclic manner, the work queue entries indicating work to be performed associated with the packets, dequeue respective ones of the work queue entries read from the work queue responsively to reading the respective work queue entries from the work queue, add the work queue entries to an execution database used to track execution of the work queue entries, and execute the work queue entries in the execution database.

公开(公告)号：US11909855B2

公开(公告)日：2024-02-20

申请号：US18075460

申请日：2022-12-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Miriam Menes ,  Noam Bloch ,  Adi Menachem ,  Idan Burstein ,  Ariel Shahar ,  Maxim Fudim

IPC: H04L9/06 ,  H04L9/08 ,  H04L9/32

CPC classification number: H04L9/0625 ,  H04L9/0861 ,  H04L9/3247

Abstract: In one embodiment, data communication apparatus includes packet processing circuitry to receive data from a memory responsively to a data transfer request, and cryptographically process the received data in units of data blocks using a block cipher so as to add corresponding cryptographically processed data blocks to a sequence of data packets, the sequence including respective ones of the cryptographically processed data blocks having block boundaries that are not aligned with payload boundaries of respective one of the packets, such that respective ones of the cryptographically processed data blocks are divided into two respective segments, which are contained in successive respective ones of the packets in the sequence, and a network interface which includes one or more ports for connection to a packet data network and is configured to send the sequence of data packets to a remote device over the packet data network via the one or more ports.

公开(公告)号：US11876885B2

公开(公告)日：2024-01-16

申请号：US17335122

申请日：2021-06-01

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Ariel Shahar ,  Shahaf Shuler ,  Ariel Almog ,  Eitan Hirshberg ,  Natan Manevich

IPC: H04L7/00

CPC classification number: H04L7/0091

Abstract: A timing system including timing circuitry which includes an arming queue, a clock work queue, and a clock completion queue. At least the clock work queue is to provide timing information, and the arming queue is to arm the clock work queue. Related apparatus and methods are also provided.

公开(公告)号：US11822973B2

公开(公告)日：2023-11-21

申请号：US16571220

申请日：2019-09-16

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Ariel Shahar ,  Ahmad Omary

IPC: G06F9/46 ,  G06F9/52

CPC classification number: G06F9/522

Abstract: A method including an executing entity, including fencing dependency circuitry, communicating with physical memory including a work queue (WQ) including a first controlling work request (WR), and a first dependent WR, the first dependent WR including a fencing indication indicating that the first dependent WR should not be executed until the first controlling WR has completed, the fencing dependency circuitry determining that the first dependent WR is ready for execution and checking, based on the fencing indication in the first dependent WR, whether the first controlling WR has completed, and the executing entity executing the first dependent WR only when the first controlling WR has completed. Related apparatus and methods are also provided.

公开(公告)号：US11762773B2

公开(公告)日：2023-09-19

申请号：US17863453

申请日：2022-07-13

Applicant: Mellanox Technologies, Ltd.

Inventor： Daniel Marcovitch ,  Gil Bloch ,  Richard Graham ,  Ariel Shahar ,  Roee Moyal ,  Igor Voks

IPC: G06F12/0813 ,  G06F12/06 ,  G06F9/54 ,  G06F9/50

CPC classification number: G06F12/0813 ,  G06F9/5011 ,  G06F9/544 ,  G06F12/063 ,  G06F2209/508

Abstract: A network device in a communication network includes a controller and processing circuitry. The controller is configured to manage execution of an operation whose execution depends on inputs from a group of one or more work-request initiators. The processing circuitry is configured to read one or more values, which are set by the work-request initiators in one or more memory locations that are accessible to the work-request initiators and to the network device, and to trigger execution of the operation in response to verifying that the one or more values read from the one or more memory locations indicate that the work-request initiators in the group have provided the respective inputs.

公开(公告)号：US11683266B2

公开(公告)日：2023-06-20

申请号：US17963216

申请日：2022-10-11

Applicant: Mellanox Technologies, Ltd.

Inventor： Boris Pismenny ,  Miriam Menes ,  Idan Burstein ,  Liran Liss ,  Noam Bloch ,  Ariel Shahar

IPC: H04L45/00 ,  H04L45/42 ,  G06F11/10 ,  H04L69/163 ,  H04L69/22

CPC classification number: H04L45/566 ,  G06F11/1004 ,  H04L45/38 ,  H04L45/42 ,  H04L69/163 ,  H04L69/22

Abstract: A system includes a host processor, which has a host memory and is coupled to store data in a non-volatile memory in accordance with a storage protocol. A network interface controller (NIC) receives data packets conveyed over a packet communication network from peer computers containing, in payloads of the data packets, data records that encode data in accordance with the storage protocol for storage in the non-volatile memory. The NIC processes the data records in the data packets that are received in order in each flow from a peer computer and extracts and writes the data to the host memory, and when a data packet arrives out of order, writes the data packet to the host memory without extracting the data and processes the data packets in the flow so as to recover context information for use in processing the data records in subsequent data packets in the flow.

公开(公告)号：US10757183B2

公开(公告)日：2020-08-25

申请号：US15924293

申请日：2018-03-19

Applicant: Mellanox Technologies, Ltd.

Inventor： Ariel Shahar ,  Shahaf Shuler ,  Lion Levi

IPC: H04L29/08 ,  H04L1/16 ,  H04L12/931

Abstract: A method for communication includes receiving in a computer system a request from a peer computer system. Upon finding that the computer system is currently not ready to process the request, a Negative Acknowledgement (NAK) message is sent from the computer system to the peer computer system, at a sending time that is derived from a time at which the computer system is ready to process the request.