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公开(公告)号：US20240097876A1
公开(公告)日：2024-03-21
申请号：US18523991
申请日：2023-11-30
发明人： Dotan David Levi , Ariel Shahar , Shahaf Shuler , Ariel Almog , Eitan Hirshberg , Natan Manevich
IPC分类号： H04L7/00
CPC分类号： H04L7/0091
摘要： A communication system includes at least one send queue, containing send queue entries pointing to packets to be transmitted over a network by packet sending circuitry. A clock work queue contains clock queue entries to synchronize sending times of the packets pointed to by the send queue entries. At least one arming queue contains arming queue entries to arm the clock work queue at selected time intervals.
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公开(公告)号：US11870590B2
公开(公告)日：2024-01-09
申请号：US17107990
申请日：2020-12-01
发明人： Idan Burstein , Roee Moyal , Ariel Shahar , Noam Bloch , Ran Koren
IPC分类号： H04L1/18 , H04L1/1829 , G06F15/173
CPC分类号： H04L1/1829 , G06F15/17331
摘要： A method for data transfer includes transmitting a sequence of data packets from a first computer over a network to a second computer in a single RDMA data transfer transaction. Upon receipt of a second packet in the sequence without previously having received the first packet, the second computer sends a NAK packet over the network to the first computer, indicating that the first packet was not received. A retransmission mode is selected responsively to the type of the transaction, such that when the transaction is of a first type, the first packet is retransmitted from the first computer to the second computer in response to the NAK packet without retransmitting the second packet, and when the transaction is of a second type, both the first and second packets are retransmitted from the first computer to the second computer in response to the NAK packet.
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公开(公告)号：US20230418746A1
公开(公告)日：2023-12-28
申请号：US17958697
申请日：2022-10-03
发明人： Omri Kahalon , Avi Urman , Ilan Pardo , Omer Cohen , Sayantan Sur , Barak Biber , Saar Tarnopolsky , Ariel Shahar
IPC分类号： G06F12/0802 , G06F9/48
CPC分类号： G06F12/0802 , G06F9/4881 , G06F2212/60
摘要： A method includes receiving a network packet into a hardware pipeline of a network device; parsing and retrieving information of the network packet; determining, by the hardware pipeline, a packet-processing action to be performed by matching the information to a data structure of a set of flow data structures; sending, by the hardware pipeline, an action request to a programmable core, the action request being populated with data to trigger the programmable core to execute a hardware thread to perform a job, which is associated with the packet-processing action and that generates contextual data; retrieving the contextual data updated by the programmable core; and integrating the contextual data into performing the packet-processing action.
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公开(公告)号：US11741232B2
公开(公告)日：2023-08-29
申请号：US17163599
申请日：2021-02-01
发明人： Mor Hoyda Sfadia , Yuval Itkin , Ahmad Atamli , Ariel Shahar , Yaniv Strassberg , Itsik Levi
CPC分类号： G06F21/572 , G06F8/65 , G06F9/445 , G06F2221/033
摘要： A computer system includes a volatile memory and at least one processor. The volatile memory includes a protected storage segment (PSS) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.
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公开(公告)号：US20230133439A1
公开(公告)日：2023-05-04
申请号：US17536141
申请日：2021-11-29
IPC分类号： G06F12/0882 , G06F12/0831 , G06F13/16
摘要： A compute node includes a memory, a processor and a peripheral device. The memory is to store memory pages. The processor is to run software that accesses the memory, and to identify one or more first memory pages that are accessed by the software in the memory. The peripheral device is to directly access one or more second memory pages in the memory of the compute node using Direct Memory Access (DMA), and to notify the processor of the second memory pages that are accessed using DMA. The processor is further to maintain a data structure that tracks both (i) the first memory pages as identified by the processor and (ii) the second memory pages as notified by the peripheral device.
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公开(公告)号：US20220283964A1
公开(公告)日：2022-09-08
申请号：US17189303
申请日：2021-03-02
发明人： Idan Burstein , Dotan David Levi , Ariel Shahar , Lior Narkis , Igor Voks , Noam Bloch , Shay Aisman
IPC分类号： G06F13/16 , G06F13/38 , G06F13/42 , G06F12/1045 , G06F15/173 , G06F9/46 , G06F9/455
摘要： A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.
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公开(公告)号：US11323372B2
公开(公告)日：2022-05-03
申请号：US16853783
申请日：2020-04-21
发明人： Avi Urman , Lior Narkis , Ariel Shahar
IPC分类号： H04L45/7453 , H04L47/22
摘要： In one embodiment, a network device includes an interface configured to receive a data packet including a header section, at least one parser to parse the data of the header section yielding a first header portion and a second header portion, a packet processing engine to fetch a first match-and-action table, match a first index having a corresponding first steering action entry in the first match-and-action table responsively to the first header portion, compute a cumulative lookup value based on the first header portion and the second header portion responsively to the first steering action entry, fetch a second match-and-action table responsively to the first steering action entry, match a second index having a corresponding second steering action entry in the second match-and-action table responsively to the cumulative lookup value, and steering the packet responsively to the second steering action entry.
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公开(公告)号：US11102129B2
公开(公告)日：2021-08-24
申请号：US16559640
申请日：2019-09-04
发明人： Idan Burstein , Noam Bloch , Roee Moyal , Ariel Shahar , Yamin Friedman , Yuval Shpigelman
IPC分类号： H04L12/28 , H04L12/801 , H04L12/927 , H04L12/863 , H04L29/08 , H04L12/841
摘要： A network adapter includes circuitry and one or more ports. The ports connect to a communication network including multiple network elements. The circuitry accesses outbound messages that are pending to be sent over the communication network to multiple remote nodes via the ports. At least some of the outbound messages request the remote nodes to send respective amounts of data back to the network adapter. Based on the amounts of data requested by the outbound messages, the circuitry forecasts a bandwidth of inbound response traffic, which is expected to traverse a selected network element in response to the outbound messages toward the network adapter, determines a schedule for transmitting the outbound messages to the remote nodes so that the forecasted bandwidth meets a bandwidth supported by the selected network element, and transmits the outbound messages to the remote nodes in accordance with the determined schedule.
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9.发明授权公开(公告)号：US10824469B2
公开(公告)日：2020-11-03
申请号：US16202132
申请日：2018-11-28
发明人： Eitan Hirshberg , Ariel Shahar , Najeeb Darawshy , Omri Kahalon
摘要： A computer system includes one or more processors, one or more hardware accelerators, and control circuitry. The processors are configured to run software that executes tasks in a normal mode. The accelerators are configured to execute the tasks in an accelerated mode. The control circuitry is configured to receive one or more flows of tasks for execution by the processors and the accelerators, assign one or more initial tasks of each flow for execution by the processors, assign subsequent tasks of each flow for execution by the accelerators, and verify, for each flow, that the accelerators do not execute the subsequent tasks of the flow until the processors have fully executed the initial tasks of the flow.
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公开(公告)号：US20190132085A1
公开(公告)日：2019-05-02
申请号：US15796803
申请日：2017-10-29
发明人： Alexander Shpiner , Adi Menachem , Eitan Zahavi , Noam Bloch , Ariel Shahar
摘要： A network element processes a data flow in accordance with a communications protocol in which respective incremental sequence numbers are assigned to segments of the data flow. The segments are sent from the network element to the other network element in order of the sequence numbers, and respective acknowledgements are received from the other network element. The acknowledgements may include the highest sequence number of the segments of the flow that were received in the other network element. After transmitting the last segment of the data flow an additional segment is sent to the other network element. When it is determined from an acknowledgement of the additional segment that the last segment of the data flow was not received by the other network element, the last segment is retransmitted.
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