Signal derotating receiver
    1.
    发明授权
    Signal derotating receiver 失效
    信号解旋转接收机

    公开(公告)号:US08331491B2

    公开(公告)日:2012-12-11

    申请号:US10340577

    申请日:2003-01-10

    IPC分类号: H04L27/00

    摘要: A receiver, for example a receiver of broadcast digital terrestrial television signals modulated using COFDM (Coded Orthogonal Frequency Division Multiplexing), imposes a phase adjustment on a received signal. Phase adjustment may be effected, for example, by sample alignment of the signal, such as for cyclic prefix removal, or by shifting a window setting for a Fast Fourier Transform (FFT) processor. Before channel estimation or decoding is performed on the information stream, the information stream is derotated to compensate for the phase adjustment previously imposed on the received signal.

    摘要翻译: 接收机,例如使用COFDM(编码正交频分复用)调制的广播数字地面电视信号的接收机对接收到的信号施加相位调整。 相位调整可以例如通过信号的采样对齐来实现,例如用于循环前缀去除,或通过移位用于快速傅里叶变换(FFT)处理器的窗口设置。 在对信息流执行信道估计或解码之前,消除信息流以补偿先前对接收到的信号施加的相位调整。

    Single chip VLSI implementation of a digital receiver employing orthogonal frequency division multiplexing
    2.
    发明授权
    Single chip VLSI implementation of a digital receiver employing orthogonal frequency division multiplexing 有权
    采用正交频分复用的数字接收机的单芯片VLSI实现

    公开(公告)号:US06687315B2

    公开(公告)日:2004-02-03

    申请号:US09995011

    申请日:2001-11-27

    IPC分类号: H03D100

    摘要: The invention provides a single chip implementation of a digital receiver for multicarrier signals that are transmitted by orthogonal frequency division multiplexing. Improved channel estimation and correction circuitry are provided. The receiver has highly accurate sampling rate control and frequency control circuitry. BCH decoding of tps data carriers is achieved with minimal resources with an arrangement that includes a small Galois field multiplier. An improved FFT window synchronization circuit is coupled to the resampling circuit for locating the boundary of the guard interval transmitted with the active frame of the signal. A real-time pipelined FFT processor is operationally associated with the FFT window synchronization circuit and operates with reduced memory requirements.

    摘要翻译: 本发明提供了通过正交频分复用传输的用于多载波信号的数字接收机的单芯片实现。 提供改进的信道估计和校正电路。 接收机具有高精度的采样率控制和频率控制电路。 使用包括小伽罗瓦域乘法器的布置的最小资源来实现tps数据载体的BCH解码。 改进的FFT窗口同步电路耦合到重采样电路,用于定位与信号的有效帧一起发送的保护间隔的边界。 实时流水线FFT处理器与FFT窗口同步电路可操作地相关联,并以较少的存储器要求进行操作。

    Method and apparatus for a multicarrier receiver circuit with guard interval size detection
    3.
    发明授权
    Method and apparatus for a multicarrier receiver circuit with guard interval size detection 有权
    一种具有保护间隔大小检测的多载波接收机电路的方法和装置

    公开(公告)号:US07206361B2

    公开(公告)日:2007-04-17

    申请号:US10170165

    申请日:2002-06-12

    IPC分类号: H04L27/00

    摘要: A method and apparatus for a multicarrier receiver circuit with guard interval size detection is described. The invention allows the FFT size and guard interval size to be detected quickly, even in the presence of relatively noisy input signals. The method is robust in noisy environments, and also sufficiently robust to process signals having severe multipath and/or co-channel interference. Moreover, the method is of low complexity, and can be implemented in a VLSI circuit.

    摘要翻译: 描述了一种具有保护间隔大小检测的多载波接收机电路的方法和装置。 本发明允许快速检测FFT大小和保护间隔大小,即使存在相对噪声的输入信号。 该方法在噪声环境下是鲁棒的,并且对于具有严重的多路径和/或同频道干扰的信号来说也是足够稳健的。 此外,该方法复杂度低,可以在VLSI电路中实现。

    Method and apparatus for a multicarrier receiver circuit with guard interval size detection
    4.
    发明授权
    Method and apparatus for a multicarrier receiver circuit with guard interval size detection 有权
    一种具有保护间隔大小检测的多载波接收机电路的方法和装置

    公开(公告)号:US07916815B2

    公开(公告)日:2011-03-29

    申请号:US11685196

    申请日:2007-03-12

    IPC分类号: H04L27/06

    摘要: A method and apparatus for a multicarrier receiver circuit with guard interval size detection described. The invention allows the FFT size and guard interval size to be detected quickly even in the presence of relatively noisy input signals. The method is robust in noise environments, and also sufficiently robust to process signals having severe multipath and/or co-channel interference. Moreover, the method is of low complexity, and can be implemented in a VLSI circuit.

    摘要翻译: 一种用于具有保护间隔尺寸检测的多载波接收机电路的方法和装置。 本发明允许即使在存在相对嘈杂的输入信号的情况下也能快速地检测FFT大小和保护间隔大小。 该方法在噪声环境中是鲁棒的,并且对于处理具有严重的多径和/或同信道干扰的信号也是足够鲁棒的。 此外,该方法复杂度低,可以在VLSI电路中实现。

    Method and Apparatus for a Multicarrier Receiver Circuit With Guard Interval Size Detection
    5.
    发明申请
    Method and Apparatus for a Multicarrier Receiver Circuit With Guard Interval Size Detection 有权
    用于具有保护间隔尺寸检测的多载波接收器电路的方法和装置

    公开(公告)号:US20080107214A1

    公开(公告)日:2008-05-08

    申请号:US11685196

    申请日:2007-03-12

    IPC分类号: H04L27/06

    摘要: A method and apparatus for a multicarrier receiver circuit with guard interval size detection described. The invention allows the FFT size and guard interval size to be detected quickly even in the presence of relatively noisy input signals. The method is robust in noise environments, and also sufficiently robust to process signals having severe multipath and/or co-channel interference. Moreover, the method is of low complexity, and can be implemented in a VLSI circuit.

    摘要翻译: 一种用于具有保护间隔尺寸检测的多载波接收机电路的方法和装置。 本发明允许即使在存在相对嘈杂的输入信号的情况下也能快速地检测FFT大小和保护间隔大小。 该方法在噪声环境中是鲁棒的,并且对于处理具有严重的多径和/或同信道干扰的信号也是足够鲁棒的。 此外,该方法复杂度低,可以在VLSI电路中实现。

    Galois field multiplier for Reed-Solomon decoder
    6.
    发明授权
    Galois field multiplier for Reed-Solomon decoder 失效
    Reed-Solomon解码器的Galois域乘法器

    公开(公告)号:US5818855A

    公开(公告)日:1998-10-06

    申请号:US801544

    申请日:1997-02-18

    申请人: Thomas Foxcroft

    发明人: Thomas Foxcroft

    CPC分类号: H03M13/151 G06F7/724

    摘要: A Reed-Solomon decoder includes an optimized Galois Field multiplication circuit. The circuit has a plurality of multipliers, connected in a linear chain, wherein a first multiplicand of the first multiplier is the magnitude A, and the second multiplicand is a constant. The circuit operates on a linear combination of alpha values that sum to .alpha..sup.j, each multiplier in the chain generating a succeeding alpha value. A plurality of selectors enable the outputs of the multipliers according to the magnitude .alpha..sup.j. An addition circuit, preferably realized as a logical network of XOR gates, is connected to the selectors for adding the enabled outputs of the multipliers to form the final product.

    摘要翻译: 里德 - 所罗门解码器包括优化的伽罗瓦域乘法电路。 该电路具有以线性链连接的多个乘法器,其中第一乘法器的第一被乘数为幅度A,第二被乘数为常数。 该电路以与alpha j相加的α值的线性组合运行,链中的每个乘数产生后续的α值。 多个选择器使能乘法器的输出根据幅度αj。 优选地实现为XOR门的逻辑网络的加法电路连接到选择器,用于添加乘法器的使能输出以形成最终产品。

    Receiver circuit
    7.
    发明授权
    Receiver circuit 有权
    接收电路

    公开(公告)号:US07349497B1

    公开(公告)日:2008-03-25

    申请号:US09617587

    申请日:2000-07-18

    IPC分类号: H04L27/06

    摘要: A receiver circuit is for processing a received signal which includes at least a first portion and a second portion which repeats the content of the first portion after a repeat interval. For example, the receiver may be for DVB-T signals using COFDM. In order to ensure that the estimated symbol start position is accurate, the receiver calculates two correlation values, namely an early correlation and a late correlation. The early correlation is measured between samples ahead of an assumed first portion start position and ahead of an assumed second portion start position, and the late correlation is measured between samples behind an assumed first portion end position and behind an assumed second portion end position. When the assumed start and end positions are accurate, the early and late correlations are equal, and so the assumed start and end positions are controlled to equalize the early correlation and the late correlation.

    摘要翻译: 接收机电路用于处理接收信号,该接收信号至少包括在重复间隔之后重复第一部分的内容的第一部分和第二部分。 例如,接收机可以是使用COFDM的DVB-T信号。 为了确保估计的符号开始位置是准确的,接收机计算两个相关值,即早期相关和晚期相关。 在假设的第一部分开始位置之前的样品之前并且在假定的第二部分开始位置之前的样品之间测量早期相关性,并且在假设的第一部分结束位置之后的样本之后和假定的第二部分结束位置之后测量后期相关性。 当假设的起始和终点位置准确时,早期和晚期相关性相等,因此假定的起始和终止位置被控制以平衡早期相关性和晚期相关性。